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PSD4256G6V
Flash In-System Programmable (ISP) Peripherals for 16-bit MCUs
PRELIMINARY DATA
FEATURES SUMMARY PSD provides an integrated solution to 16-bit MCU-based applications that includes configurable memories, PLD logic, and I/O: s Dual bank Flash memories - 8Mbits of Primary Flash Memory (16 uniform sectors, 64Kbyte) - 512Kbits of Secondary Flash Memory with 4 sectors - Concurrent operation: READ from one memory while erasing and writing the other
s s
s
High Endurance: - 100,000 Erase/WRITE Cycles of Flash Memory - 1,000 Erase/WRITE Cycles of PLD - 15 Year Data Retention
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Single Supply Voltage - 3V (+20%/-10%) Memory Speed - 100ns Flash memory and SRAM access time for VCC = 3V (+20%/-10%) - 90ns Flash memory and SRAM access time for VCC = 3.3V (+/-10%)
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256Kbits of SRAM (battery-backed) PLD with Macrocells - Over 3000 Gates of PLD: CPLD and DPLD - CPLD with 16 Output Macrocells (OMCs) and 24 Input Macrocells (IMCs) - DPLD - user defined internal chip select decoding
Figure 1. 80-lead, Thin, Quad, Flat Package
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Seven l/O Ports with 52 I/O pins: 52 individually configurable I/O port pins that can be used for the following functions: - MCU I/Os - PLD I/Os - Latched MCU address output - Special function I/Os - l/O ports may be configured as open-drain outputs
TQFP80 (U)
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In-System Programming (ISP) with JTAG - Built-in JTAG compliant serial port allows fullchip In-System Programmability - Efficient manufacturing allow easy product testing and programming - Use low cost FlashLINK cable with PC
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Page Register - Internal page register that can be used to expand the microcontroller address space by a factor of 256
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Programmable power management
1/100
December 2002
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
PSD4256G6V
TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 In-System Programming (ISP) via JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 PSDsoft . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Logic Diagram (Figure 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pin Names (Table 1.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 TQFP80 Connections (Figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 TQFP80 Pin Description (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 PSD Block Diagram (Figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PSD ARCHITECTURAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 MCU Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 ISP via JTAG Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PLD I/O (Table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 JTAG Signals on Port E (Table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 In-System Programming (ISP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 In-Application Programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Methods of Programming Different Functional Blocks of the PSD (Table 5.) . . . . . . . . . . . . . . . . . 17 DEVELOPMENT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 PSDsoft Development Tool (Figure 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 PSD REGISTER DESCRIPTION AND ADDRESS OFFSETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Register Address Offset (Table 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 REGISTER BIT DEFINITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Data-In Registers - Ports A, B, C, D, E, F, and G (Table 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Data-Out Registers - Ports A, B, C, D, E, F, and G (Table 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Direction Registers - Ports A, B, C, D, E, F, and G (Table 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Control Registers - Ports E, F, and G (Table 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Drive Registers - Ports A, B, D, E, and G (Table 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Enable-Out Registers - Ports A, B, C, and F (Table 12.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Input Macrocells - Ports A, B, and C (Table 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Output Macrocells A Register (Table 14.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Out Macrocells B Register (Table 15.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Mask Macrocells A Register (Table 16.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Mask Macrocells B Register (Table 17.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2/100
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
PSD4256G6V
Flash Memory Protection Register 1 (Table 18.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Flash Memory Protections Register 2 (Table 19.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Flash Boot Protection Register (Table 20.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 JTAG Enable Register (Table 21.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Page Register (Table 22.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 PMMR0 Register (Table 23.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 PMMR2 Register (Table 24.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 VM Register (Table 25.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Memory_ID0 Register (Table 26.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Memory_ID1 Register (Table 27.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 DETAILED OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Memory Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Memory Block Size and Organization (Table 28.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Primary Flash Memory and Secondary Flash memory Description. . . . . . . . . . . . . . . . . . . . . . . . . 26 Ready/Busy (PE4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Memory Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 16-bit Instructions (Table 29.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Power-up Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 READ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 READ Memory Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 READ Primary Flash Identifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 READ Memory Sector Protection Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Reading the Erase/Program Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Status Bits (Table 30.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Status Bits for Motorola 16-bit MCU (Table 31.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Data Polling (DQ7) - DQ15 for Motorola . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Toggle Flag (DQ6) - DQ14 for Motorola . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Error Flag (DQ5) - DQ13 for Motorola . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Erase Time-out Flag (DQ3) - DQ11 for Motorola . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 PROGRAMMING FLASH MEMORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Data Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Data Polling Flowchart (Figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Data Toggle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Unlock Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Data Toggle Flowchart (Figure 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3/100
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
PSD4256G6V
ERASING FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Flash Bulk Erase . . . . . . . . . . . . . . . . . . . . . Flash Sector Erase . . . . . . . . . . . . . . . . . . . Suspend Sector Erase. . . . . . . . . . . . . . . . . Resume Sector Erase . . . . . . . . . . . . . . . . . ...... ...... ...... ...... ....... ....... ....... ....... ...... ...... ...... ...... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... . . . . 33 . . . . 33 . . . . 33 . . . . 33
SPECIFIC FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Flash Memory Sector Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 RESET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Reset (RESET) Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 MEMORY SELECT SIGNALS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Priority Level of Memory and I/O Components (Figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Configuration Modes for MCUs with Separate Program and Data Spaces . . . . . . . . . . . . . . . . . . . 36 Combined Space Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 80C31 Memory Map Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8031 Memory Modules - Separate Space (Figure 9.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8031 Memory Modules - Combined Space (Figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 PAGE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Page Register (Figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 MEMORY ID REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 The Turbo Bit in PSD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 DPLD and CPLD Inputs (Table 32.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 PLD Diagram (Figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 DECODE PLD (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 DPLD Logic Array (Figure 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 COMPLEX PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Macrocell and I/O Port (Figure 14.) . . . . . . . . . . . . . . . . . . . . . . . . . . Output Macrocell (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Macrocell Port and Data Bit Assignments (Table 33.) . . . . . . Product Term Allocator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... .... .... .... .... 41 42 42 43
4/100
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
PSD4256G6V
Loading and Reading the Output Macrocells (OMC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 The OMC Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 The Output Enable of the OMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 CPLD Output Macrocell (Figure 15.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Input Macrocell (Figure 16.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 External Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 External Chip Select Signal (Figure 17.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Handshaking Communication Using Input Macrocells (Figure 18.). . . . . . . . . . . . . . . . . . . . . . . . . 46 MCU BUS INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 16-bit MCUs and Their Control Signals (Table 34.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 PSD Interface to a Multiplexed Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 An Example of a Typical Multiplexed Bus Interface (Figure 19.) . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 PSD Interface to a Non-Multiplexed, 16-bit Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 An Example of a Typical Non-Multiplexed Bus Interface (Figure 20.) . . . . . . . . . . . . . . . . . . . . . . . 49 Data Byte Enable Reference for a 16-bit Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 16-Bit Data Bus with BHE (Table 35.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 16-bit MCU Bus Interface Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 16-Bit Data Bus with WRH and WRL (Table 36.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 16-Bit Data Bus with SIZ0, A0 (Motorola MCU) (Table 37.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 16-Bit Data Bus with LDS, UDS (Motorola MCU) (Table 38.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 80C196 and 80C186 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Interfacing the PSD with an 80C196 (Figure 21.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 MC683xx and MC68HC16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Interfacing the PSD with an MC68331 (Figure 22.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 80C51XA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Interfacing the PSD with an 80C51XA-G3 (Figure 23.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 H8/300 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Interfacing the PSD with an H83/2350 (Figure 24.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 MMC2001 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 C16x Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Interfacing the PSD with an MMC2001 (Figure 25.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Interfacing the PSD with a C167CR (Figure 26.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 General Port Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Port Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 General I/O Port Architecture (Figure 27.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 MCU I/O Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 PLD I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Address Out Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Port Operating Modes (Table 39.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Port Operating Mode Settings (Table 40.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 I/O Port Latched Address Output Assignments (Table 41.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Address In Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
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Data Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Peripheral I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Peripheral I/O Mode (Figure 28.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 JTAG In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 MCU RESET Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Port Configuration Registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Port Configuration Registers (PCR) (Table 42.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Drive Select Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Port Pin Direction Control, Output Enable P.T. Not Defined (Table 43.) . . . . . . . . . . . . . . . . . . . . . 64 Port Pin Direction Control, Output Enable P.T. Defined (Table 44.) . . . . . . . . . . . . . . . . . . . . . . . . 64 Port Direction Assignment Example (Table 45.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Drive Register Pin Assignment (Table 46.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Data In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Data Out Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Output Macrocells (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Mask Macrocell Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Port Data Registers (Table 47.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Enable Out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Ports A, B and C - Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Port A, B, and C Structure (Figure 29.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Port D - Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Port D Structure (Figure 30.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Port E - Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Port F - Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Port G - Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Port E, F, and G Structure (Figure 31.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
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POWER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Automatic Power-down (APD) Unit and Power-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Power-down Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Effect of Power-down Mode on Ports (Table 48.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 APD Unit (Figure 32.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 PSD Timing and Standby Current During Power-down Mode (Table 49.) . . . . . . . . . . . . . . . . . . . 71 Other Power Saving Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 PLD Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 SRAM Standby Mode (Battery Backup) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 PSD Chip Select Input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Input Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Enable Power-down Flow Chart (Figure 33.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Input Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 ADP Counter Operation (Table 50.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 RESET TIMING AND DEVICE STATUS AT RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Power-on RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Warm RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 I/O Pin, Register and PLD Status at RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 RESET of Flash Memory Erase and Program Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Status During Power-on RESET, Warm RESET, and Power-down Mode (Table 51.) . . . . . . . . . . 74 Reset (RESET) Timing (Figure 34.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . 75 Standard JTAG Signals . . . . . . . . . . . . . . . . JTAG Extensions . . . . . . . . . . . . . . . . . . . . . Security and Flash memory Protection . . . . JTAG Port Signals (Table 52.). . . . . . . . . . . ...... ...... ...... ...... ....... ....... ....... ....... ...... ...... ...... ...... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... . . . . 75 . . . . 76 . . . . 76 . . . . 76
INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 AC/DC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 PLD ICC / Frequency Consumption (Figure 35.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Example of PSD Typical Power Calculation at VCC = 3.0V (with Turbo Mode On) (Table 53.) . . . 78 Example of PSD Typical Power Calculation at VCC = 3.0V (with Turbo Mode Off) (Table 54.) . . . 79 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Absolute Maximum Ratings (Table 55.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
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DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Operating Conditions (Table 56.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 AC Symbols for PLD Timing (Table 57.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 AC Measurement Conditions (Table 58.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Capacitance (Table 59.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 AC Measurement I/O Waveform (Figure 36.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 AC Measurement Load Circuit (Figure 37.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Switching Waveforms - Key (Figure 38.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 DC Characteristics (Table 60.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Input to Output Disable / Enable (Figure 39.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 CPLD Combinatorial Timing (Table 61.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 CPLD Macrocell Synchronous Clock Mode Timing (Table 62.) . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 CPLD Macrocell Asynchronous Clock Mode Timing (Table 63.). . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Synchronous Clock Mode Timing - PLD (Figure 40.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Asynchronous RESET / Preset (Figure 41.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Asynchronous Clock Mode Timing (product term clock) (Figure 42.) . . . . . . . . . . . . . . . . . . . . . . . 86 Input Macrocell Timing (Product Term Clock) (Figure 43.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Input Macrocell Timing (Table 64.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Program, WRITE and Erase Times (Table 65.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Peripheral I/O WRITE Timing Diagram (Figure 44.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 READ Timing Diagram (Figure 45.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 READ Timing (Table 66.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 WRITE Timing Diagram (Figure 46.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 WRITE Timing (Table 67.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Peripheral I/O READ Timing Diagram (Figure 47.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Port F Peripheral Data Mode READ Timing (Table 68.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Port F Peripheral Data Mode WRITE Timing (Table 69.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Power-down Timing (Table 70.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Reset (RESET) Timing (Table 71.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Reset (RESET) Timing Diagram (Figure 48.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 VSTBYON Timing (Table 72.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 ISC Timing Diagram (Figure 49.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 ISC Timing (Table 73.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Pin Assignments - PSD4256G6V TQFP80 (Table 76.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
PSD4256G6V
SUMMARY DESCRIPTION The PSD family of memory systems for microcontrollers (MCUs) brings In-System-Programmability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. PSD devices combine many of the peripheral functions found in MCU based applications. PSD devices integrate an optimized Macrocell logic architecture. The Macrocell was created to address the unique requirements of embedded system designs. It allows direct connection between the system address/data bus, and the internal PSD registers, to simplify communication between the MCU and other supporting devices. The PSD family offers two methods to program the PSD Flash memory while the PSD is soldered to the circuit board: In-System Programming (ISP) via JTAG, and In-Application Programming (IAP). In-System Programming (ISP) via JTAG An IEEE 1149.1 compliant JTAG In-System Programming (ISP) interface is included on the PSD enabling the entire device (Flash memories, PLD, configuration) to be rapidly programmed while soldered to the circuit board. This requires no MCU participation, which means the PSD can be programmed anytime, even when completely blank. The innovative JTAG interface to Flash memories is an industry first, solving key problems faced by designers and manufacturing houses, such as: First time programming. How do I get firmware into the Flash memory the very first time? JTAG is the answer. Program the blank PSD with no MCU involvement. Inventory build-up of pre-programmed devices. How do I maintain an accurate count of preprogrammed Flash memory and PLD devices based on customer demand? How many and what version? JTAG is the answer. Build your hardware with blank PSDs soldered directly to the board and then custom program just before they are shipped to the customer. No more labels on chips, and no more wasted inventory. Expensive sockets. How do I eliminate the need for expensive and unreliable sockets? JTAG is the answer. Solder the PSD directly to the circuit board. Program first time and subsequent times
with JTAG. No need to handle devices and bend the fragile leads. In-Application Programming (IAP) Two independent Flash memory arrays are included so that the MCU can execute code from one while erasing and programming the other. Robust product firmware updates in the filed are possible over any communication channel (e.g., CAN, Ethernet, UART, J1850) using this unique architecture. Designers are relieved of these problems: Simultaneous READ and WRITE to Flash memory. How can the MCU program the same memory from which it executing code? It cannot. The PSD allows the MCU to operate the two Flash memory blocks concurrently, reading code from one while erasing and programming the other during IAP. Complex memory mapping. How can I map these two memories efficiently? A programmable Decode PLD (DPLD) is embedded in the PSD MODULE. The concurrent PSD memories can be mapped anywhere in MCU address space, segment by segment with extremely high address resolution. As an option, the secondary Flash memory can be swapped out of the system memory map when IAP is complete. A built-in page register breaks the MCU address limit. Separate Program and Data space. How can I write to Flash memory while it resides in Program space during field firmware updates? My 80C51XA will not allow it. The PSD provides means to reclassify Flash memory as Data space during IAP, then back to Program space when complete. PSDsoft PSDsoft, a software development tool from ST, guides you through the design process step-bystep making it possible to complete an embedded MCU design capable of ISP/IAP in just hours. Select your MCU and PSDsoft takes you through the remainder of the design with point and click entry, covering PSD selection, pin definitions, programmable logic inputs and outputs, MCU memory map definition, ANSI-C code generation for your MCU, and merging your MCU firmware with the PSD design. When complete, two different device programmers are supported directly from PSDsoft: FlashLINK (JTAG) and PSDpro.
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PSD4256G6V
Figure 2. Logic Diagram
VCC
Table 1. Pin Names
PA0-PA7 PB0-PB7 Port-A Port-B Port-C Port-D Port-E Port-F Port-G Address/Data Control Reset Supply Voltage Ground
8 PA0-PA7 8 PB0-PB7 3 CNTL0CNTL2 4 PSD4xxxGx 16 AD0-AD15 8 RESET 8 PG0-PG7 PF0-PF7 8 PE0-PE7 PD0-PD3 8 PC0-PC7
PC0-PC7 PD0-PD3 PE0-PE7 PF0-PF7 PG0-PG7 AD0-AD15 CNTL0-CNTL2 RESET VCC VSS
VSS
AI04916
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PSD4256G6V
Figure 3. TQFP80 Connections
70 GND
69 VCC 68 PB7
80 PD1
79 PD0
67 PB6
66 PB5
65 PB4
64 PB3
63 PB2
62 PB1
PD2 1 PD3 2 AD0 3 AD1 4 AD2 5 AD3 6 AD4 7 GND 8 VCC 9 AD5 10 AD6 11 AD7 12 AD8 13 AD9 14 AD10 15 AD11 16 AD12 17 AD13 18 AD14 19 AD15 20
61 PB0
78 PE7
77 PE6
76 PE5
75 PE4
74 PE3
73 PE2
72 PE1
71 PE0
60 CNTL1 59 CNTL0 58 PA7 57 PA6 56 PA5 55 PA4 54 PA3 53 PA2 52 PA1 51 PA0 50 GND 49 GND 48 PC7 47 PC6 46 PC5 45 PC4 44 PC3 43 PC2 42 PC1 41 PC0
PG0 21
PG1 22
PG2 23
PG3 24
PG4 25
PG5 26
PG6 27
PG7 28
VCC 29
GND 30
PF0 31
PF1 32
PF2 33
PF3 34
PF4 35
PF5 36
PF6 37
PF7 38
RESET 39
CNTL2 40
AI04943
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PSD4256G6V
Table 2. TQFP80 Pin Description
Pin Name Pin Type Description This is the lower Address/Data port. Connect your MCU address or address/data bus according to the following rules: 1. If your MCU has a multiplexed address/data bus where the data is multiplexed with the lower address bits, connect AD0-AD7 to this port. 2. If your MCU does not have a multiplexed address/data bus, connect A0-A7 to this port. 3. If you are using an 80C51XA in burst mode, connect A4/D0 through A11/D7 to this port. ALE or AS latches the address. The PSD drives data out only if the READ signal is active and one of the PSD functional blocks has been selected. The addresses on this port are passed to the PLDs. This is the upper Address/Data port. Connect your MCU address or address/data bus according to the following rules: 1. If your MCU has a multiplexed address/data bus where the data is multiplexed with the address bits, connect A8-A15 or AD8-AD15 to this port. 2. If your MCU does not have a multiplexed address/data bus, connect A8-A15 to this port. 3. If you are using an 80C51XA in burst mode, connect A12/D8 through A19/D15 to this port. ALE or AS latches the address. The PSD drives data out only if the READ signal is active and one of the PSD functional blocks has been selected. The addresses on this port are passed to the PLDs. The following control signals can be connected to this pin, based on your MCU: 1. WR - active Low, WRITE Strobe input. 2. R_W - active High, READ/active Low WRITE input. 3. WRL - active Low, WRITE to Low-byte. This pin is connected to the PLDs. Therefore, these signals can be used in decode and other logic equations. The following control signals can be connected to this pin, based on your MCU: 1. 1RD - active Low, READ Strobe input. 2. E - E clock input. 3. DS - active Low, Data Strobe input. 4. LDS - active Low, Strobe for low data byte. This pin is connected to the PLDs. Therefore, these signals can be used in decode and other logic equations. READ or other Control input pin, with multiple configurations. Depending on the MCU interface selected, this pin can be: 1. PSEN - Program Select Enable, active Low in code retrieve bus cycle (80C51XA mode). 2. BHE - High-byte enable, 16-bit data bus. 3. UDS - active Low, Strobe for high data byte, 16-bit data bus mode. 4. SIZ0 - Byte enable input. 5. LSTRB - Low Strobe input. This pin is also connected to the PLDs. Active Low input. Resets I/O Ports, PLD Macrocells and some of the Configuration Registers and JTAG registers. Must be Low at Power-up. RESET also aborts any Flash memory Program or Erase cycle that is currently in progress. These pins make up Port A. These port pins are configurable and can have the following functions: 1. MCU I/O - standard output or input port. 2. CPLD Macrocell (McellA0-McellA7) outputs. 3. Latched, transparent or registered PLD inputs (can also be PLD input for address A16 and above).
ADIO0ADIO7
3-7 10-12
I/O
ADIO8ADIO15
13-20
I/O
CNTL0
59
I
CNTL1
60
I
CNTL2
40
I
RESET
39
I
PA0-PA7
51-58
I/O CMOS or Open Drain
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PSD4256G6V
Pin Name Pin Type I/O CMOS or Open Drain Description These pins make up Port B. These port pins are configurable and can have the following functions: 1. MCU I/O - standard output or input port. 2. CPLD Macrocell (McellB0-McellB7) outputs. 3. Latched, transparent or registered PLD inputs (can also be PLD input for address A16 and above). These pins make up Port C. These port pins are configurable and can have the following functions: 1. MCU I/O - standard output or input port. 2. External Chip Select (ECS0-ECS7) outputs. 3. Latched, transparent or registered PLD inputs (can also be PLD input for address A16 and above). PD0 pin of Port D. This port pin can be configured to have the following functions: 1. ALE/AS input - latches address on ADIO0-ADIO15. 2. AS input - latches address on ADIO0-ADIO15 on the rising edge. 3. MCU I/O - standard output or input port. 4. Transparent PLD input (can also be PLD input for address A16 and above). PD1 pin of Port D. This port pin can be configured to have the following functions: 1. MCU I/O - standard output or input port. 2. Transparent PLD input (can also be PLD input for address A16 and above). 3. CLKIN - clock input to the CPLD Macrocells, the APD Unit's Power-down counter, and the CPLD AND Array. PD2 pin of Port D. This port pin can be configured to have the following functions: 1. MCU I/O - standard output or input port. 2. Transparent PLD input (can also be PLD input for address A16 and above). 3. PSD Chip Select Input (CSI). When Low, the MCU can access the PSD memory and I/O. When High, the PSD memory blocks are disabled to conserve power. The falling edge of this signal can be used to get the device out of Power-down mode. PD3 pin of Port D. This port pin can be configured to have the following functions: 1. MCU I/O - standard output or input port. 2. Transparent PLD input (can also be PLD input for address A16 and above). 3. WRH - for 16-bit data bus, WRITE to high byte, active low. PE0 pin of Port E. This port pin can be configured to have the following functions: 1. MCU I/O - standard output or input port. 2. Latched address output. 3. TMS Input for the JTAG Serial Interface. PE1 pin of Port E. This port pin can be configured to have the following functions: 1. MCU I/O - standard output or input port. 2. Latched address output. 3. TCK Input for the JTAG Serial Interface. PE2 pin of Port E. This port pin can be configured to have the following functions: 1. MCU I/O - standard output or input port. 2. Latched address output. 3. TDI input for the JTAG Serial Interface. PE3 pin of Port E. This port pin can be configured to have the following functions: 1. MCU I/O - standard output or input port. 2. Latched address output. 3. TDO output for the JTAG Serial Interface.
PB0-PB7
61-68
PC0-PC7
41-48
I/O CMOS
PD0
79
I/O CMOS or Open Drain I/O CMOS or Open Drain I/O CMOS or Open Drain I/O CMOS or Open Drain I/O CMOS or Open Drain I/O CMOS or Open Drain I/O CMOS or Open Drain I/O CMOS or Open Drain
PD1
80
PD2
1
PD3
2
PE0
71
PE1
72
PE2
73
PE3
74
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PSD4256G6V
Pin Name Pin Type I/O CMOS or Open Drain I/O CMOS or Open Drain I/O CMOS or Open Drain I/O CMOS or Open Drain Description PE4 pin of Port E. This port pin can be configured to have the following functions: 1. MCU I/O - standard output or input port. 2. Latched address output. 3. TSTAT output for the JTAG Serial Interface. 4. Ready/Busy output for parallel In-System Programming (ISP). PE5 pin of Port E. This port pin can be configured to have the following functions: 1. MCU I/O - standard output or input port. 2. Latched address output. 3. TERR active Low output for the JTAG Serial Interface. PE6 pin of Port E. This port pin can be configured to have the following functions: 1. MCU I/O - standard output or input port. 2. Latched address output. 3. VSTBY - SRAM standby voltage input for SRAM battery backup. PE7 pin of Port E. This port pin can be configured to have the following functions: 1. MCU I/O - standard output or input port. 2. Latched address output. 3. Battery-on Indicator (VBATON). Goes High when power is being drawn from the external battery. These pins make up Port F. These port pins are configurable and can have the following functions: 1. MCU I/O - standard output or input port. 2. External Chip Select (ECS0-ECS7) outputs, or inputs to CPLD. 3. Latched address outputs. 4. Address A1-A3 inputs in 80C51XA mode (PF0 is grounded) 5. Data bus port (D0-D7) in a non-multiplexed bus configuration. 6. Peripheral I/O mode. 7. MCU RESET Mode. These pins make up Port G. These port pins are configurable and can have the following functions: 1. MCU I/O - standard output or input port. 2. Latched address outputs. 3. Data bus port (D8-D15) in a non-multiplexed, 16-bit bus configuration. 4. MCU RESET Mode. Supply Voltage
PE4
75
PE5
76
PE6
77
PE7
78
PF0-PF7
31-38
I/O CMOS or Open Drain
PG0-PG7
21-28
I/O CMOS or Open Drain
VCC
9, 29, 69 8, 30, 49, 50, 70
GND
Ground pins
Note: Signal names that have multiple names or functions are defined using PSDsoft.
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ADDRESS/DATA/CONTROL BUS
PLD INPUT BUS PAGE REGISTER EMBEDDED ALGORITHM 16 SECTORS 8 MBIT PRIMARY FLASH MEMORY
POWER MANGMT UNIT
VSTDBY (PE6 )
Figure 4. PSD Block Diagram
8
CNTL0, CNTL1, CNTL2 SECTOR SELECTS FLASH DECODE PLD (DPLD) 82 SECTOR SELECTS SRAM SELECT ADIO PORT CSIOP RUNTIME CONTROL AND I/O REGISTERS 8 EXT CS TO PORT C or F 16 OUTPUT MACROCELLS PORT A & B 24 INPUT MACROCELLS CLKIN PROG. PORT PORT G CLKIN MACROCELL FEEDBACK OR PORT INPUT PORT F PORT A ,B & C PERIP I/O MODE SELECTS 256 KBIT BATTERY BACKUP SRAM PROG. MCU BUS INTRF. 512 KBIT SECONDARY FLASH MEMORY (BOOT OR DATA) 4 SECTORS
AD0 - AD15
PROG. PORT PORT A
PA0 - PA7
PF0 - PF7 PORT F
Note: Additional address lines can be brought in to the device via Port A, B, C, D, or F.
PROG. PORT 82 FLASH ISP CPLD (CPLD) PROG. PORT PORT B PB0 - PB7 PROG. PORT PORT C PC0 - PC7 PROG. PORT PORT D PD0 - PD3 CLKIN GLOBAL CONFIG. & SECURITY PLD, CONFIGURATION & FLASH MEMORY LOADER JTAG SERIAL CHANNEL PROG. PORT PORT E PE0 - PE7
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
PG0 - PG7
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PSD4256G6V
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PSD4256G6V
PSD ARCHITECTURAL OVERVIEW PSD devices contain several major functional blocks. Figure 4, page 15 shows the architecture of the PSD device family. The functions of each block are described briefly in the following sections. Many of the blocks perform multiple functions and are user configurable. Memory Each of the memory blocks is briefly discussed in the following paragraphs. A more detailed discussion can be found in the section entitled "Memory Blocks" on page 25. The 8Mbit primary Flash memory is the main memory of the PSD. It is divided into 16 equallysized sectors that are individually selectable. The 512Kbit secondary Flash memory is divided into 4 sectors. Each sector is individually selectable. The 256Kbit SRAM is intended for use as a scratch-pad memory or as an extension to the MCU SRAM. If an external battery is connected to the PSD's Voltage Standby (VSTBY, PE6) signal, data is retained in the event of power failure. Each memory block can be located in a different address space as defined by the user. The access times for all memory types includes the address latching and DPLD decoding time. PLDs The device contains two PLD blocks, the Decode PLD (DPLD) and the Complex PLD (CPLD), as shown in Table 2, page 12, each optimized for a different function. The functional partitioning of the PLDs reduces power consumption, optimizes cost/performance, and eases design entry. The DPLD is used to decode addresses and to generate Sector Select signals for the PSD internal memory and registers. The DPLD has combinatorial outputs, while the CPLD can implement more general user-defined logic functions. The CPLD has 16 Output Macrocells (OMC) and 8 combinatorial outputs. The PSD also has 24 Input Macrocells (IMC) that can be configured as inputs to the PLDs. The PLDs receive their inputs from the PLD Input Bus and are differentiated by their output destinations, number of product terms, and Macrocells. The PLDs consume minimal power. The speed and power consumption of the PLD is controlled by the Turbo Bit in PMMR0 and other bits in PMMR2. These registers are set by the MCU at
run-time. There is a slight penalty to PLD propagation time when not in the Turbo mode. I/O Ports The PSD has 52 I/O pins divided among seven ports (Port A, B, C, D, E, F, and G). Each I/O pin can be individually configured for different functions. Ports can be configured as standard MCU I/ O ports, PLD I/O, or latched address outputs for MCUs using multiplexed address/data buses. The JTAG pins can be enabled on Port E for InSystem Programming (ISP). MCU Bus Interface The PSD easily interfaces with most 8-bit or 16-bit MCUs, either with multiplexed or non-multiplexed address/data buses. The device is configured to respond to the MCU's control pins, which are also used as inputs to the PLDs. ISP via JTAG Port In-System Programming (ISP) can be performed through the JTAG signals on Port E. This serial interface allows complete programming of the entire PSD MODULE device. A blank device can be completely programmed. The JTAG signals (TMS, TCK, TSTAT, TERR, TDI, TDO) can be multiplexed with other functions on Port E. Table 3 indicates the JTAG pin assignments. Table 3. PLD I/O
Name Decode PLD (DPLD) Complex PLD (CPLD) Inputs 82 82 Outputs 17 24 Product Terms 43 150
Table 4. JTAG Signals on Port E
Port E Pins PE0 PE1 PE2 PE3 PE4 PE5 TMS TCK TDI TDO TSTAT TERR JTAG Signal
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PSD4256G6V
In-System Programming (ISP) Using the JTAG signals on Port E, the entire PSD device (memory, logic, configuration) can be programmed or erased without the use of the MCU. In-Application Programming (IAP) The primary Flash memory can also be programmed, or re-programmed, in-system by the MCU executing the programming algorithms out of the secondary Flash memory, or SRAM. The secondary Flash memory can be programmed the same way by executing out of the primary Flash memory. Table 5, page 17 indicates which programming methods can program different functional blocks of the PSD. Page Register The 8-bit Page Register expands the address range of the MCU by up to 256 times. The paged address can be used as part of the address space to access external memory and peripherals, or internal memory and I/O. The Page Register can also be used to change the address mapping of
the Flash memory blocks into different memory spaces for IAP. Power Management Unit (PMU) The Power Management Unit (PMU) gives the user control of the power consumption on selected functional blocks based on system requirements. The PMU includes an Automatic Power-down (APD) Unit that turns off device functions during MCU inactivity. The APD Unit has a Power-down mode that helps reduce power consumption. The PSDalso has some bits that are configured at run-time by the MCU to reduce power consumption of the CPLD. The Turbo Bit in PMMR0 can be reset to '0' and the CPLD latches its outputs and goes to Standby Mode until the next transition on its inputs. Additionally, bits in PMMR2 can be set by the MCU to block signals from entering the CPLD to reduce power consumption. See the section entitled "POWER MANAGEMENT" on page 70 for more details.
Table 5. Methods of Programming Different Functional Blocks of the PSD
Functional Block Primary Flash Memory Secondary Flash memory PLD Array (DPLD and CPLD) PSD Configuration JTAG-ISP Yes Yes Yes Yes Device Programmer Yes Yes Yes Yes IAP Yes Yes No No
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PSD4256G6V
DEVELOPMENT SYSTEM The PSD family is supported by PSDsoft, a Windows-based software development tool (Windows-95, Windows-98, Windows-NT). A PSD design is quickly and easily produced in a point and click environment. The designer does not need to enter Hardware Description Language (HDL) equations, unless desired, to define PSD pin functions and memory map information. The general design flow is shown in Figure 5. PSDsoft is available from our web site (the address is given Figure 5. PSDsoft Development Tool
Choose MCU and PSD
Automatically configures MCU bus interface and other PSD attributes
on the back page of this data sheet) or other distribution channels. PSDsoft directly supports two low cost device programmers form ST: PSDpro and FlashLINK (JTAG). Both of these programmers may be purchased through your local distributor/representative, or directly from our web site using a credit card. The PSD is also supported by third party device programmers. See our web site for the current list.
Define PSD Pin and Node Functions
Point and click definition of PSD pin functions, internal nodes, and MCU system memory map
Define General Purpose Logic in CPLD
Point and click definition of combinatorial and registered logic in CPLD. Access HDL is available if needed
C Code Generation
GENERATE C CODE SPECIFIC TO PSD FUNCTIONS
Merge MCU Firmware with PSD Configuration
A composite object file is created containing MCU firmware and PSD configuration
MCU FIRMWARE HEX OR S-RECORD FORMAT
USER'S CHOICE OF MICROCONTROLLER COMPILER/LINKER
*.OBJ FILE
PSD Programmer
PSDPro, or FlashLINK (JTAG)
*.OBJ FILE AVAILABLE FOR 3rd PARTY PROGRAMMERS (CONVENTIONAL or JTAG-ISC)
AI04919
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PSD4256G6V
PSD REGISTER DESCRIPTION AND ADDRESS OFFSETS Table 6 shows the offset addresses to the PSD Table 6 provides brief descriptions of the registers registers relative to the CSIOP base address. The in CSIOP space. The following sections give a CSIOP space is the 256 bytes of address that is almore detailed description. located by the user to the internal PSD registers. Table 6. Register Address Offset
Register Name Data In Control Data Out Direction Drive Select Input Macrocell Enable Out Output Macrocells A Output Macrocells B Mask Macrocells A Mask Macrocells B Flash Memory Protection 1 Flash Memory Protection 2 Flash Boot Protection JTAG Enable PMMR0 PMMR2 Page VM Memory_ID0 Memory_ID1
Note: 1. Other registers that are not part of the I/O ports.
Port Port Port Port Port Port Port Other(1) A B C D E F G 00 01 10 11 30 32 04 06 08 0A 0C 20 21 22 23 C0 C1 C2 C7 B0 B4 E0 E2 F0 F1 05 07 09 0B 0D 1C 14 16 15 17 19 1A 4C 34 36 38 40 42 44 46 41 43 45 47 49
Description Reads Port pin as input, MCU I/O input mode Selects mode between MCU I/O or Address Out Stores data for output to Port pins, MCU I/O output mode Configures Port pin as input or output Configures Port pins as either CMOS or Open Drain Reads Input Macrocells Reads the status of the output enable to the I/ O Port driver READ - reads output of Macrocells A WRITE - loads Macrocell Flip-flops READ - reads output of Macrocells B WRITE - loads Macrocell Flip-flops Blocks writing to the Output Macrocells A Blocks writing to the Output Macrocells B Read only - Primary Flash Sector Protection Read only - Primary Flash Sector Protection Read only - PSD Security and Secondary Flash memory Sector Protection Enables JTAG Port Power Management Register 0 Power Management Register 2 Page Register Places PSD memory areas in Program and/ or Data space on an individual basis. Read only - SRAM and Primary memory size Read only - Secondary memory type and size
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PSD4256G6V
REGISTER BIT DEFINITION All the registers of the PSD are included here, for reference. Detailed descriptions of these registers can be found in the following sections. Table 7. Data-In Registers - Ports A, B, C, D, E, F, and G
Bit 7 Port pin 7 Bit 6 Port pin 6 Bit 5 Port pin 5 Bit 4 Port pin 4 Bit 3 Port pin 3 Bit 2 Port pin 2 Bit 1 Port pin 1 Bit 0 Port pin 0
Note: Bit Definitions (Read only registers): READ Port pin status when Port is in MCU I/O input mode.
Table 8. Data-Out Registers - Ports A, B, C, D, E, F, and G
Bit 7 Port pin 7 Bit 6 Port pin 6 Bit 5 Port pin 5 Bit 4 Port pin 4 Bit 3 Port pin 3 Bit 2 Port pin 2 Bit 1 Port pin 1 Bit 0 Port pin 0
Note: Bit Definitions: Latched data for output to Port pin when pin is configured in MCU I/O output mode.
Table 9. Direction Registers - Ports A, B, C, D, E, F, and G
Bit 7 Port pin 7 Bit 6 Port pin 6 Bit 5 Port pin 5 Bit 4 Port pin 4 Bit 3 Port pin 3 Bit 2 Port pin 2 Bit 1 Port pin 1 Bit 0 Port pin 0
Note: Bit Definitions: Portpin 0 = Port pin is configured in Input mode (default). Portpin 1 = Port pin is configured in Output mode.
Table 10. Control Registers - Ports E, F, and G
Bit 7 Port pin 7 Bit 6 Port pin 6 Bit 5 Port pin 5 Bit 4 Port pin 4 Bit 3 Port pin 3 Bit 2 Port pin 2 Bit 1 Port pin 1 Bit 0 Port pin 0
Note: Bit Definitions: Portpin 0 = Port pin is configured in MCU I/O mode (default). Portpin 1 = Port pin is configured in Latched Address Out mode.
Table 11. Drive Registers - Ports A, B, D, E, and G
Bit 7 Port pin 7 Bit 6 Port pin 6 Bit 5 Port pin 5 Bit 4 Port pin 4 Bit 3 Port pin 3 Bit 2 Port pin 2 Bit 1 Port pin 1 Bit 0 Port pin 0
Note: Bit Definitions: Portpin 0 = Port pin is configured for CMOS Output driver (default). Portpin 1 = Port pin is configured for Open Drain output driver.
Table 12. Enable-Out Registers - Ports A, B, C, and F
Bit 7 Port pin 7 Bit 6 Port pin 6 Bit 5 Port pin 5 Bit 4 Port pin 4 Bit 3 Port pin 3 Bit 2 Port pin 2 Bit 1 Port pin 1 Bit 0 Port pin 0
Note: Bit Definitions (Read only registers): Portpin 0 = Port pin is in tri-state driver (default). Portpin 1 = Port pin is enabled.
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PSD4256G6V
Table 13. Input Macrocells - Ports A, B, and C
Bit 7 IMcell 7 Bit 6 IMcell 6 Bit 5 IMcell 5 Bit 4 IMcell 4 Bit 3 IMcell 3 Bit 2 IMcell 2 Bit 1 IMcell 1 Bit 0 IMcell 0
Note: Bit Definitions (Read only registers): READ Input Macrocell (IMC7-IMC0) status on Ports A, B, and C.
Table 14. Output Macrocells A Register
Bit 7 Mcella 7 Bit 6 Mcella 6 Bit 5 Mcella 5 Bit 4 Mcella 4 Bit 3 Mcella 3 Bit 2 Mcella 2 Bit 1 Mcella 1 Bit 0 Mcella 0
Note: Bit Definitions: WRITE Register: Load MCellA7-MCellA0 with '0' or '1.' READ Register: Read MCellA7-MCellA0 output status.
Table 15. Out Macrocells B Register
Bit 7 Mcellb 7 Bit 6 Mcellb 6 Bit 5 Mcellb 5 Bit 4 Mcellb 4 Bit 3 Mcellb 3 Bit 2 Mcellb 2 Bit 1 Mcellb 1 Bit 0 Mcellb 0
Note: Bit Definitions: WRITE Register: Load MCellB7-MCellB0 with '0' or '1.' READ Register: Read MCellB7-MCellB0 output status.
Table 16. Mask Macrocells A Register
Bit 7 Mcella 7 Bit 6 Mcella 6 Bit 5 Mcella 5 Bit 4 Mcella 4 Bit 3 Mcella 3 Bit 2 Mcella 2 Bit 1 Mcella 1 Bit 0 Mcella 0
Note: Bit Definitions: McellA_Prot 0 = Allow MCellA flip-flop to be loaded by MCU (default). McellA_Prot 1 = Prevent MCellA flip-flop from being loaded by MCU.
Table 17. Mask Macrocells B Register
Bit 7 Mcellb 7 Bit 6 Mcellb 6 Bit 5 Mcellb 5 Bit 4 Mcellb 4 Bit 3 Mcellb 3 Bit 2 Mcellb 2 Bit 1 Mcellb 1 Bit 0 Mcellb 0
Note: Bit Definitions: McellB_Prot 0 = Allow MCellB flip-flop to be loaded by MCU (default). McellB_Prot 1 = Prevent MCellB flip-flop from being loaded by MCU.
Table 18. Flash Memory Protection Register 1
Bit 7 Sec7_Prot Bit 6 Sec6_Prot Bit 5 Sec5_Prot Bit 4 Sec4_Prot Bit 3 Sec3_Prot Bit 2 Sec2_Prot Bit 1 Sec1_Prot Bit 0 Sec0_Prot
Note: Bit Definitions (Read only register): Sec_Prot 1 = Primary Flash memory Sector is write protected. Sec_Prot 0 = Primary Flash memory Sector is not write protected.
Table 19. Flash Memory Protections Register 2
Bit 7 Sec15_Prot Bit 6 Sec14_Prot Bit 5 Sec13_Prot Bit 4 Sec12_Prot Bit 3 Sec11_Prot Bit 2 Sec10_Prot Bit 1 Sec9_Prot Bit 0 Sec8_Prot
Note: Bit Definitions (Read only register): Sec_Prot 1 = Primary Flash memory Sector is write protected. Sec_Prot 0 = Primary Flash memory Sector is not write protected.
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Table 20. Flash Boot Protection Register
Bit 7 Security_Bit Bit 6 not used Bit 5 not used Bit 4 not used Bit 3 Sec3_Prot Bit 2 Sec2_Prot Bit 1 Sec1_Prot Bit 0 Sec0_Prot
Note: Bit Definitions: Sec_Prot 1 = Secondary Flash memory Sector is write protected. Sec_Prot 0 = Secondary Flash memory Sector is not write protected. Security_Bit 0 = Security Bit in device has not been set. Security_Bit 1 = Security Bit in device has been set.
Table 21. JTAG Enable Register
Bit 7 not used Bit 6 not used Bit 5 not used Bit 4 not used Bit 3 not used Bit 2 not used Bit 1 not used Bit 0 JTAGEnable
Note: Bit Definitions: JTAGEnable 1 = JTAG Port is enabled. JTAGEnable 0 = JTAG Port is disabled.
Table 22. Page Register
Bit 7 PGR 7 Bit 6 PGR 6 Bit 5 PGR 5 Bit 4 PGR 4 Bit 3 PGR 3 Bit 2 PGR 2 Bit 1 PGR 1 Bit 0 PGR 0
Note: Bit Definitions: Configure Page input to PLD. Default is PGR7-PGR0 = '0.'
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Table 23. PMMR0 Register
Bit 7 not used (set to 0) Bit 6 not used (set to 0) Bit 5 PLD MCells CLK Bit 4 PLD Array CLK Bit 3 PLD Turbo Bit 2 not used (set to 0) Bit 1 APD Enable Bit 0 not used (set to 0)
Note: The bits of this register are cleared to zero following power-up. Subsequent Reset (RESET) pulses do not clear the registers. Bit Definitions: APD Enable 0 = Automatic Power-down (APD) is disabled. 1 = Automatic Power-down (APD) is enabled. PLD Turbo 0 = PLD Turbo is on. 1 = PLD Turbo is off, saving power. PLD Array CLK 0 = CLKIN to the PLD AND array is connected. Every CLKIN change powers up the PLD when Turbo Bit is off. 1 = CLKIN to the PLD AND array is disconnected, saving power. PLD MCells CLK 0 = CLKIN to the PLD Macrocells is connected. 1 = CLKIN to the PLD Macrocells is disconnected, saving power.
Table 24. PMMR2 Register
Bit 7 not used (set to 0) Bit 6 PLD Array WRH Bit 5 PLD Array ALE Bit 4 PLD Array CNTL2 Bit 3 PLD Array CNTL1 Bit 2 PLD Array CNTL0 Bit 1 not used (set to 0) Bit 0 PLD Array Addr
Note: For Bit 4, Bit 3, Bit 2: See Table 34, page 47 for the signals that are blocked on pins CNTL0-CNTL2. Bit Definitions: PLD Array Addr 0 = Address A7-A0 are connected to the PLD array. 1 = Address A7-A0 are blocked from the PLD array, saving power. Note: In X A Mode, A3-A0 come from PF3-PF0, and A7-A4 come from ADIO7-ADIO4. PLD Array CNTL2 0 = CNTL2 input to the PLD AND array is connected. 1 = CNTL2 input to the PLD AND array is disconnected, saving power. PLD Array CNTL1 0 = CNTL1 input to the PLD AND array is connected. 1 = CNTL1 input to the PLD AND array is disconnected, saving power. PLD Array CNTL0 0 = CNTL0 input to the PLD AND array is connected. 1 = CNTL0 input to the PLD AND array is disconnected, saving power. PLD Array ALE 0 = ALE input to the PLD AND array is connected. 1 = ALE input to the PLD AND array is disconnected, saving power. PLD Array WRH 0 = WRH/DBE input to the PLD AND array is connected. 1 = WRH/DBE input to the PLD AND array is disconnected, saving power.
Table 25. VM Register
Bit 7 Peripheral mode Bit 6 not used (set to 0) Bit 5 not used (set to 0) Bit 4 FL_data Bit 3 Boot_data Bit 2 FL_code Bit 1 Boot_code Bit 0 SR_code
Note: On RESET, Bits 1-4 are loaded to configurations that are selected by the user in PSDsoft. Bit 0 and Bit 7 are always cleared on RESET. Bit 0-4 are active only when the device is configured in 8051 Mode. Bit Definitions: SR_code 0 = PSEN cannot access SRAM in 80C51XA modes. 1 = PSEN can access SRAM in 80C51XA modes. Boot_Code 0 = PSEN cannot access Secondary NVM in 80C51XA modes. 1 = PSEN can access Secondary NVM in 80C51XA modes. FL_Code 0 = PSEN cannot access Primary Flash memory in 80C51XA modes. 1 = PSEN can access Primary Flash memory in 80C51XA modes. Boot_data 0 = RD cannot access Secondary NVM in 80C51XA modes. 1 = RD can access Secondary NVM in 80C51XA modes. FL_data 0 = RD cannot access Primary Flash memory in 80C51XA modes. 1 = RD can access Primary Flash memory in 80C51XA modes. Peripheral mode 0 = Peripheral mode of Port F is disabled. 1 = Peripheral mode of Port F is enabled.
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Table 26. Memory_ID0 Register
Bit 7 S_size 3 Bit 6 S_size 2 Bit 5 S_size 1 Bit 4 S_size 0 Bit 3 F_size 3 Bit 2 F_size 2 Bit 1 F_size 1 Bit 0 F_size 0
Note: Bit Definitions: F_size[3:0]
S_size[3:0]
0h = There is no Primary Flash memory 1h = Primary Flash memory size is 256Kbit 2h = Primary Flash memory size is 512Kbit 3h = Primary Flash memory size is 1Mbit 4h = Primary Flash memory size is 2Mbit 5h = Primary Flash memory size is 4Mbit 6h = Primary Flash memory size is 8Mbit 0h = There is no SRAM 1h = SRAM size is 16Kbit 2h = SRAM size is 32Kbit 3h = SRAM size is 64Kbit 4h = SRAM size is 128Kbit 5h = SRAM size is 256Kbit
Table 27. Memory_ID1 Register
Bit 7 not used (set to 0) Bit 6 not used (set to 0) Bit 5 B_type 1 Bit 4 B_type 0 Bit 3 B_size 3 Bit 2 B_size 2 Bit 1 B_size 1 Bit 0 B_size 0
Note: Bit Definitions: F_size[3:0]
S_size[3:0]
0h = There is no Secondary NVM 1h = Secondary NVM size is 128Kbit 2h = Secondary NVM size is 256Kbit 3h = Secondary NVM size is 512Kbit 0h = Secondary NVM is Flash memory 1h = Secondary NVM is EEPROM
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DETAILED OPERATION As shown in Figure 4, page 15, the PSD consists of six major types of functional blocks: s Memory Blocks
s s s s s
MCU Bus Interface I/O Ports Power Management Unit (PMU) JTAG-ISP Interface The functions of each block are described in the following sections. Many of the blocks perform multiple functions, and are user configurable.
Memory Blocks The PSD has the following memory blocks: - Primary Flash memory - Secondary Flash memory - SRAM The Memory Select signals for these blocks originate from the Decode PLD (DPLD) and are userdefined in PSDsoft. Table 28 summarizes the sizes and organizations of the memory blocks.
Table 28. Memory Block Size and Organization
Primary Flash Memory Sector Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Total Sector Size (Bytes) 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 1024K Sector Select Signal FS0 FS1 FS2 FS3 FS4 FS5 FS6 FS7 FS8 FS9 FS10 FS11 FS12 FS13 FS14 FS15 16 Sectors 64K 4 Sectors 32K Secondary Flash Memory Sector Size (Bytes) 16K 8K 8K 32K Sector Select Signal CSBOOT0 CSBOOT1 CSBOOT2 CSBOOT3 SRAM SRAM Size (Bytes) 32K SRAM Select Signal RS0
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Primary Flash Memory and Secondary Flash memory Description The primary Flash memory is divided evenly into 8 a Flash memory block is being written to, or when a Flash memory block is being erased. The output sectors. The secondary Flash memory is divided is a '1' (Ready) when no WRITE or Erase cycle is into 4 sectors of different size. Each sector of eiin progress. ther memory block can be separately protected from Program and Erase cycles. Memory Operation Flash memory may be erased on a sector-by-secThe primary Flash memory and secondary Flash tor basis, and programmed word-by-word. Flash memory are addressed through the MCU Bus Insector erasure may be suspended while data is terface. The MCU can access these memories in read from other sectors of the block and then reone of two ways: sumed after reading. s The MCU can execute a typical bus WRITE or During a Program or Erase cycle in Flash memory, READ operation just as it would if accessing a the status can be output on the Ready/Busy pin RAM or ROM device using standard bus cycles. (PE4). This pin is set up using PSDsoft. s The MCU can execute a specific instruction that Memory Block Select Signals consists of several WRITE and READ operations. This involves writing specific data The DPLD generates the Select signals for all the patterns to special addresses within the Flash internal memory blocks (see the section entitled memory to invoke an embedded algorithm. "PLDs", on page 38). Each of the sectors of the priThese instructions are summarized in Table 29, mary Flash memory has a Select signal (FS0page 27. FS15) which can contain up to three product terms. Each of the sectors of the secondary Flash Typically, the MCU can read Flash memory using memory has a Select signal (CSBOOT0READ operations, just as it would read a ROM deCSBOOT3) which can contain up to three product vice. However, Flash memory can only be erased terms. Having three product terms for each Select and programmed using specific instructions. For signal allows a given sector to be mapped in differexample, the MCU cannot write a single byte dient areas of system memory. When using a MCU rectly to Flash memory as one would write a byte with separate Program and Data space to RAM. To program a word into Flash memory, (80C51XA), these flexible Select signals allow dythe MCU must execute a Program instruction, then namic re-mapping of sectors from one memory test the status of the Programming event. This staspace to the other before and after IAP. The tus test is achieved by a READ operation or polling SRAM block has a single Select signal (RS0). Ready/Busy (PE4). Ready/Busy (PE4) Flash memory can also be read by using special instructions to retrieve particular Flash device inThis signal can be used to output the Ready/Busy formation (sector protect status and ID). status of the PSD. The output is a '0' (Busy) when
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Table 29. 16-bit Instructions
Instruction(14) READ(5) READ Main Flash ID(6, 13) READ Sector Protection(6,8,13) Program a Flash Word(13) Flash Sector Erase(7,13) Flash Bulk Erase(13) Suspend Sector Erase(11) Resume Sector Erase(12) RESET(6) Unlock Bypass Unlock Bypass Program(9) Unlock Bypass Reset(10) FS0-FS15 or CSBOOT0CSBOOT3 1 0 Cycle 1 "Read" RD @ RA AAh@ XAAAh AAh@ XAAAh AAh@ XAAAh AAh@ XAAAh AAh@ XAAAh B0h@ XXXXh 30h@ XXXXh F0h@ XXXXh AAh@ XAAAh A0h@ XXXXh 90h@ XXXXh 55h@ X554h PD@ PA 00h@ XXXXh 20h@ XAAAh 55h@ X554h 55h@ X554h 55h@ X554h 55h@ X554h 55h@ X554h 90h@ XAAAh 90h@ XAAAh A0h@ XAAAh 80h@ XAAAh 80h@ XAAAh Read ID @ XX02h Read 00h or 01h @ XX04h PD@ PA AAh@ XAAAh AAh@ XAAAh 55h@ X554h 55h@ X554h 30h@ SA 10h@ XAAAh 30h(7)@ next SA Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7
1
1 1 1 1 1 1 1 1 1
Note: 1. All bus cycles are WRITE bus cycles, except the ones with the "Read" label 2. All values are in hexadecimal: X = "Don't care." Addresses of the form XXXXh, in this table, must be even addresses RA = Address of the memory location to be read RD = Data read from location RA during the READ cycle PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of WRITE Strobe (WR, CNTL0). PA is an even address for PSD in word programming mode. PD = Data word to be programmed at location PA. Data is latched on the rising edge of WRITE Strobe (WR, CNTL0) SA = Address of the sector to be erased or verified. The Sector Select (FS0-FS15 or CSBOOT0-CSBOOT3) of the sector to be erased, or verified, must be Active (High). 3. Sector Select (FS0 to FS15 or CSBOOT0 to CSBOOT3) signals are active High, and are defined in PSDsoft. 4. Only address bits A11-A0 are used in instruction decoding. 5. No Unlock or instruction cycles are required when the device is in the READ Mode 6. The RESET instruction is required to return to the READ Mode after reading the Flash ID, or after reading the Sector Protection Status, or if the Error Flag Bit (DQ5/DQ13) goes High. 7. Additional sectors to be erased must be written at the end of the Sector Erase instruction within 80s. 8. The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector Select is active, and (A1,A0) = (1,0). 9. The Unlock Bypass instruction is required prior to the Unlock Bypass Program instruction. 10. The Unlock Bypass Reset Flash instruction is required to return to reading memory data when the device is in the Unlock Bypass mode. 11. The system may perform READ and Program cycles in non-erasing sectors, read the Flash ID or read the Sector Protection Status when in the Suspend Sector Erase mode. The Suspend Sector Erase instruction is valid only during a Sector Erase cycle. 12. The Resume Sector Erase instruction is valid only during the Suspend Sector Erase mode. 13. The MCU cannot invoke these instructions while executing code from the same Flash memory as that for which the instruction is intended. The MCU must retrieve, for example, the code from the secondary Flash memory when reading the Sector Protection Status of the primary Flash memory. 14. All WRITE bus cycles in an instruction are byte-WRITE to an even address (XA4Ah or X554h). A Flash memory Program bus cycle writes a word to an even address.
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INSTRUCTIONS An instruction consists of a sequence of specific operations. Each received byte is sequentially decoded by the PSD and not executed as a standard WRITE operation. The instruction is executed when the correct number of bytes are properly received and the time between two consecutive bytes is shorter than the time-out period. Some instructions are structured to include READ operations after the initial WRITE operations. The instruction must be followed exactly. Any invalid combination of instruction bytes or time-out between two consecutive bytes while addressing Flash memory resets the device logic into READ Mode (Flash memory is read like a ROM device). The PSD supports the instructions summarized in Table 29, page 27: s Erase memory by chip or sector
s s s s s s
Suspend or resume sector erase Program a Word RESET to READ Mode READ Primary Flash Identifier value READ Sector Protection Status Bypass
These instructions are detailed in Table 29, page 27. For efficient decoding of the instructions, the first two bytes of an instruction are the coded cycles and are followed by an instruction byte or confirmation byte. The coded cycles consist of writing the data AAh to address XAAAh during the first cycle and data 55h to address X554h during the second cycle (unless the Bypass instruction feature is used, as described later). Address signals A15A12 are "Don't care" during the instruction WRITE cycles. However, the appropriate Sector Select signal (FS0-FS15, or CSBOOT0-CSBOOT3) must be selected. The primary and secondary Flash memories have the same instruction set (except for READ Primary Flash Identifier). The Sector Select signals determine which Flash memory is to receive and execute the instruction. The primary Flash memory is selected if any one of its Sector Select signals (FS0-FS15) is High, and the secondary Flash memory is selected if any one of its Sector Select signals (CSBOOT0-CSBOOT3) is High. Power-up Condition The PSD internal logic is reset upon Power-up to the READ Mode. Sector Select (FS0-FS15 and
CSBOOT0-CSBOOT3) must be held Low, and WRITE Strobe (WR/WRL, CNTL0) High, during Power-up for maximum security of the data contents and to remove the possibility of data being written on the first edge of WRITE Strobe (WR/ WRL, CNTL0). Any WRITE cycle initiation is locked when VCC is below V LKO. READ Under typical conditions, the MCU may read the primary Flash memory, or secondary Flash memory, using READ operations just as it would a ROM or RAM device. Alternately, the MCU may use READ operations to obtain status information about a Program or Erase cycle that is currently in progress. Lastly, the MCU may use instructions to read special data from these memory blocks. The following sections describe these READ functions. READ Memory Contents Primary Flash memory and secondary Flash memory are placed in the READ Mode after Power-up, chip reset, or a Reset Flash instruction (see Table 29, page 27). The MCU can read the memory contents of the primary Flash memory, or the secondary Flash memory by using READ operations any time the READ operation is not part of an instruction. READ Primary Flash Identifier The primary Flash memory identifier is read with an instruction composed of 4 operations: 3 specific WRITE operations and a READ operation (see Table 29, page 27). The identifier for the primary Flash memory is E7h. The secondary Flash memory does not support this instruction. READ Memory Sector Protection Status The Flash memory Sector Protection Status is read with an instruction composed of four operations: three specific WRITE operations and a READ operation (see Table 29, page 27). The READ operation produces 01h if the Flash memory sector is protected, or 00h if the sector is not protected. The sector protection status for all NVM blocks (primary Flash memory, or secondary Flash memory) can be read by the MCU accessing the Flash Protection and Flash Boot Protection registers in PSD I/O space. See the section entitled "Flash Memory Sector Protect", on page 34, for register definitions.
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Reading the Erase/Program Status Bits The PSD provides several status bits to be used by the MCU to confirm the completion of an Erase or Program cycle of Flash memory. These status bits minimize the time that the MCU spends performing these tasks and are defined in Table 30. The status byte resides in an even location, and can be read as many times as needed. Also note
that DQ15-DQ8 is an even byte for Motorola MCUs with a 16-bit data bus. For Flash memory, the MCU can perform a READ operation to obtain these status bits while an Erase or Program instruction is being executed by the embedded algorithm. See the section entitled "PROGRAMMING FLASH MEMORY", on page 31, for details.
Table 30. Status Bits
DQ7 Data Polling DQ6 Toggle Flag DQ5 Error Flag DQ4 X DQ3 Erase Timeout DQ2 X DQ1 X DQ0 X
Table 31. Status Bits for Motorola 16-bit MCU
DQ15 Data Polling DQ14 Toggle Flag DQ13 Error Flag DQ12 X DQ11 Erase Timeout DQ10 X DQ9 X DQ8 X
Notes:X = Not guaranteed value, can be read either '1' or '0.' DQ15-DQ0 represent the Data Bus bits, D15-D0. FS0-FS15/CSBOOT0-CSBOOT3 are active High.
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Data Polling (DQ7) - DQ15 for Motorola When erasing or programming in Flash memory, the Data Polling Bit (DQ7/DQ15) outputs the complement of the bit being entered for programming/ writing on the DQ7/DQ15 Bit. Once the Program instruction or the WRITE operation is completed, the true logic value is read on the Data Polling Bit (DQ7/DQ15) (in a READ operation). s Data Polling is effective after the fourth WRITE pulse (for a Program instruction) or after the sixth WRITE pulse (for an Erase instruction). It must be performed at the address being programmed or at an address within the Flash memory sector being erased. s During an Erase cycle, the Data Polling Bit (DQ7/DQ15) outputs a '0.' After completion of the cycle, the Data Polling Bit (DQ7/DQ15) outputs the last bit programmed (it is a '1' after erasing). s If the location to be programmed is in a protected Flash memory sector, the instruction is ignored. s If all the Flash memory sectors to be erased are protected, the Data Polling Bit (DQ7/DQ15) is reset to '0' for about 100s, and then returns to the value from the previously addressed location. No erasure is performed. Toggle Flag (DQ6) - DQ14 for Motorola The PSD offers another way for determining when the Flash memory Program cycle is completed. During the internal WRITE operation and when either FS0-FS15 or CSBOOT0-CSBOOT3 is true, the Toggle Flag Bit (DQ6/DQ14) toggles from 0 to '1' and '1' to '0' on subsequent attempts to read any word of the memory. When the internal cycle is complete, the toggling stops and the data read on the Data Bus D0-D7 is the value from the addressed memory location. The device is now accessible for a new READ or WRITE operation. The cycle is finished when two successive READs yield the same output data. s The Toggle Flag Bit (DQ6/DQ14) is effective after the fourth WRITE pulse (for a Program
instruction) or after the sixth WRITE pulse (for an Erase instruction). s If the location to be programmed belongs to a protected Flash memory sector, the instruction is ignored. s If all the Flash memory sectors selected for erasure are protected, the Toggle Flag Bit (DQ6/DQ14) toggles to '0' for about 100s and then returns to the value from the previously addressed location. Error Flag (DQ5) - DQ13 for Motorola During a normal Program or Erase cycle, the Error Flag Bit (DQ5/DQ13) is reset to '0.' This bit is set to '1' when there is a failure during a Flash memory Program, Sector Erase, or Bulk Erase cycle. In the case of Flash memory programming, the Error Flag Bit (DQ5/DQ13) indicates the attempt to program a Flash memory bit, or bits, from the programmed state, 0, to the erased state, '1,' which is not a valid operation. The Error Flag Bit (DQ5/ DQ13) may also indicate a Time-out condition while attempting to program a word. In case of an error in a Flash memory Sector Erase or Word Program cycle, the Flash memory sector in which the error occurred or to which the programmed location belongs must no longer be used. Other Flash memory sectors may still be used. The Error Flag Bit (DQ5/DQ13) is reset after a RESET instruction. A RESET instruction is required after detecting an error on the Error Flag Bit (DQ5/DQ13). Erase Time-out Flag (DQ3) - DQ11 for Motorola The Erase Time-out Flag Bit (DQ3/DQ11) reflects the time-out period allowed between two consecutive Sector Erase instructions. The Erase Time-out Flag Bit (DQ3/DQ11) is reset to '0' after a Sector Erase cycle for a period of 100s + 20% unless an additional Sector Erase instruction is decoded. After this period, or when the additional Sector Erase instruction is decoded, the Erase Time-out Flag Bit (DQ3/DQ11) is set to '1.'
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PROGRAMMING FLASH MEMORY Flash memory must be erased prior to being programmed. The MCU may erase Flash memory all at once or by-sector. Although erasing Flash memory occurs on a sector or device basis, programming Flash memory occurs on a word basis. The primary and secondary Flash memories require the MCU to send an instruction to program a word or to erase sectors (see Table 29, page 27). Once the MCU issues a Flash memory Program or Erase instruction, it must check the status bits for completion. The embedded algorithms that are invoked inside the PSD support several means to provide status to the MCU. Status may be checked using any of three methods: Data Polling, Data Toggle, or Ready/Busy (PE4) signal. Data Polling Polling on the Data Polling Bit (DQ7/DQ15) is a method of checking whether a Program or Erase cycle is in progress or has completed. Figure 6 shows the Data Polling algorithm. When the MCU issues a Program instruction, the embedded algorithm within the PSD begins. The MCU then reads the location of the word to be programmed in Flash memory to check the status. The Data Polling Bit (DQ7/DQ15) becomes the complement of the corresponding bit of the original data word to be programmed. The MCU continues to poll this location, comparing data and monitoring the Error Flag Bit (DQ5/DQ13). When the Data Polling Bit (DQ7/DQ15) matches the corresponding bit of the original data, and the Error Flag Bit (DQ5/DQ13) remains '0,' the embedded algorithm is complete. If the Error Flag Bit (DQ5/DQ13) is '1,' the MCU should test the Data Polling Bit (DQ7/ DQ15) again since the Data Polling Bit (DQ7/ DQ15) may have changed simultaneously with the Error Flag Bit (DQ5/DQ13) (see Figure 6). The Error Flag Bit (DQ5/DQ13) is set if either an internal time-out occurred while the embedded algorithm attempted to program the location or if the MCU attempted to program a '1' to a bit that was not erased (not erased is logic '0'). It is suggested (as with all Flash memories) to read the location again after the embedded programming algorithm has completed, to compare the word that was written to the Flash memory with the word that was intended to be written. When using the Data Polling method during an Erase cycle, Figure 6 still applies. However, the
Data Polling Bit (DQ7/DQ15) is '0' until the Erase cycle is complete. A '1' on the Error Flag Bit (DQ5/ DQ13) indicates a time-out condition on the Erase cycle, a 0 indicates no error. The MCU can read any even location within the sector being erased to get the Data Polling Bit (DQ7/DQ15) and the Error Flag Bit (DQ5/DQ13). PSDsoft generates ANSI C code functions that implement these Data Polling algorithms. Figure 6. Data Polling Flowchart
START
READ DQ5 and DQ7 (DQ13 and DQ15) at Valid Even Address
DQ7 (DQ15) = Data7 (Data15) No
Yes
No
DQ5 (DQ13) =1 Yes READ DQ7 (DQ15)
DQ7 (DQ15) = Data7 (Data15) No Program or Erase Cycle failed
Yes
Program or Erase Cycle is complete
Issue RESET instruction
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Data Toggle Checking the Toggle Flag Bit (DQ6/DQ14) is another method of determining whether a Program or Erase cycle is in progress or has completed. Figure 7 shows the Data Toggle algorithm. When the MCU issues a Program instruction, the embedded algorithm within the PSD begins. The MCU then reads the location to be programmed in Flash memory to check the status. The Toggle Flag Bit (DQ6/DQ14) toggles each time the MCU reads this location until the embedded algorithm is complete. The MCU continues to read this location, checking the Toggle Flag Bit (DQ6/DQ14) and monitoring the Error Flag Bit (DQ5/DQ13). When the Toggle Flag Bit (DQ6/DQ14) stops toggling (two consecutive READs yield the same value), and the Error Flag Bit (DQ5/DQ13) remains '0,' the embedded algorithm is complete. If the Error Flag Bit (DQ5/DQ13) is '1,' the MCU should test the Toggle Flag Bit (DQ6/DQ14) again, since the Toggle Flag Bit (DQ6/DQ14) may have changed simultaneously with the Error Flag Bit (DQ5/DQ13) (see Figure 7). The Error Flag Bit (DQ5/DQ13) is set if either an internal time-out occurred while the embedded algorithm attempted to program, or if the MCU attempted to program a '1' to a bit that was not erased (not erased is logic '0'). It is suggested (as with all Flash memories) to read the location again after the embedded programming algorithm has completed, to compare the word that was written to Flash memory with the word that was intended to be written. When using the Data Toggle method after an Erase cycle, Figure 7 still applies. the Toggle Flag Bit (DQ6/DQ14) toggles until the Erase cycle is complete. A '1' on the Error Flag Bit (DQ5/DQ13) indicates a time-out condition on the Erase cycle, a '0' indicates no error. The MCU can read any even location within the sector being erased to get the Toggle Flag Bit (DQ6/DQ14) and the Error Flag Bit (DQ5/DQ13). PSDsoft generates ANSI C code functions which implement these Data Toggling algorithms. Unlock Bypass The Unlock Bypass instruction allows the system to program words to the Flash memories faster than using the standard Program instruction. The Unlock Bypass mode is entered by first initiating two Unlock cycles. This is followed by a third WRITE cycle containing the Unlock Bypass command, 20h (as shown in Table 29, page 27). The Flash memory then enters the Unlock Bypass mode. A two-cycle Unlock Bypass Program instruction is all that is required to program in this mode. The first cycle in this instruction contains the Unlock
Bypass Program command, A0h. The second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispense with the initial two Unlock cycles required in the standard Program instruction, resulting in faster total programming time. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset instructions are valid. To exit the Unlock Bypass mode, the system must issue the two-cycle Unlock Bypass Reset instruction. The first cycle must contain the data 90h; the second cycle the data 00h. Addresses are "Don't care" for both cycles. The Flash memory then returns to READ Mode. Figure 7. Data Toggle Flowchart
START
READ DQ5 and DQ6 (DQ13 and DQ14) at Valid Even Address
DQ6 (DQ14) = Toggle Yes
No
No
DQ5 (DQ13) =1 Yes READ DQ6 (DQ14)
DQ6 (DQ14) = Toggle Yes Program or Erase Cycle failed
No
Program or Erase Cycle is complete
Issue RESET instruction
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PSD4256G6V
ERASING FLASH MEMORY Flash Bulk Erase The Flash Bulk Erase instruction uses six WRITE operations followed by a READ operation of the status register, as described in Table 29, page 27. If any byte of the Bulk Erase instruction is wrong, the Bulk Erase instruction aborts and the device is reset to the READ Memory mode. During a Bulk Erase, the memory status may be checked by reading the Error Flag Bit (DQ5/ DQ13), the Toggle Flag Bit (DQ6/DQ14), and the Data Polling Bit (DQ7/DQ15), as detailed in the section entitled "PROGRAMMING FLASH MEMORY", on page 31. The Error Flag Bit (DQ5/DQ13) returns a '1' if there has been an Erase Failure (maximum number of Erase cycles have been executed). It is not necessary to program the memory with 00h because the PSD automatically does this before erasing to 0FFh. During execution of the Bulk Erase instruction, the Flash memory does not accept any instructions. Flash Sector Erase The Sector Erase instruction uses six WRITE operations, as described in Table 29, page 27. Additional Flash Sector Erase confirm commands and Flash memory sector addresses can be written subsequently to erase other Flash memory sectors in parallel, without further coded cycles, if the additional commands are transmitted in a shorter time than the time-out period of about 100s. The input of a new Sector Erase command restarts the time-out period. The status of the internal timer can be monitored through the level of the Erase Time-out Flag Bit (DQ3/DQ11). If the Erase Time-out Flag Bit (DQ3/ DQ11) is '0,' the Sector Erase instruction has been received and the time-out period is counting. If the Erase Time-out Flag Bit (DQ3/DQ11) is '1,' the time-out period has expired and the PSD is busy erasing the Flash memory sector(s). Before and during Erase time-out, any instruction other than Suspend Sector Erase and Resume Sector Erase, abort the cycle that is currently in progress, and reset the device to READ Mode. It is not necessary to program the Flash memory sector with 00h as the PSD does this automatically before erasing. During a Sector Erase, the memory status may be checked by reading the Error Flag Bit (DQ5/ DQ13), the Toggle Flag Bit (DQ6/DQ14), and the Data Polling Bit (DQ7/DQ15), as detailed in the section entitled "PROGRAMMING FLASH MEMORY", on page 31.
During execution of the Erase cycle, the Flash memory accepts only RESET and Suspend Sector Erase instructions. Erasure of one Flash memory sector may be suspended, in order to read data from another Flash memory sector, and then resumed. Suspend Sector Erase When a Sector Erase cycle is in progress, the Suspend Sector Erase instruction can be used to suspend the cycle by writing 0B0h to any even address when an appropriate Sector Select (FS0FS15 or CSBOOT0-CSBOOT3) is High. (See Table 29, page 27). This allows reading of data from another Flash memory sector after the Erase cycle has been suspended. Suspend Sector Erase is accepted only during the Flash Sector Erase instruction execution and defaults to READ Mode. A Suspend Sector Erase instruction executed during an Erase time-out period, in addition to suspending the Erase cycle, terminates the time out period. The Toggle Flag Bit (DQ6/DQ14) stops toggling when the PSD internal logic is suspended. The status of this bit must be monitored at an address within the Flash memory sector being erased. The Toggle Flag Bit (DQ6/DQ14) stops toggling between 0.1s and 15s after the Suspend Sector Erase instruction has been executed. The PSD is then automatically set to READ Mode. If an Suspend Sector Erase instruction was executed, the following rules apply: - Attempting to read from a Flash memory sector that was being erased outputs invalid data. - Reading from a Flash memory sector that was not being erased is valid. - The Flash memory cannot be programmed, and only responds to Resume Sector Erase and RESET instructions (READ is an operation and is allowed). - If a RESET instruction is received, data in the Flash memory sector that was being erased is invalid. Resume Sector Erase If a Suspend Sector Erase instruction was previously executed, the Erase cycle may be resumed with this instruction. The Resume Sector Erase instruction consists of writing 030h to any even address while an appropriate Sector Select (FS0FS15 or CSBOOT0-CSBOOT3) is High. (See Table 29, page 27.)
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PSD4256G6V
SPECIFIC FEATURES Flash Memory Sector Protect Each sector of Primary or Secondary Flash memory can be separately protected against Program and Erase cycles. Sector Protection provides additional data security because it disables all Program or Erase cycles. This mode can be activated (or deactivated) through the JTAG-ISP Port or a Device Programmer. Sector protection can be selected for each sector using the PSDsoft program. This automatically protects selected sectors when the device is programmed through the JTAG Port or a Device Programmer. Flash memory sectors can be unprotected to allow updating of their contents using the JTAG Port or a Device Programmer. The MCU can read (but cannot change) the sector protection bits. Any attempt to program or erase a protected Flash memory sector is ignored by the device. The Verify operation results in a READ of the protected data. This allows a guarantee of the retention of the Protection status. The sector protection status can be read by the MCU through the Flash memory protection and Secondary Flash memory protection registers (in the CSIOP block) or use the READ Sector Protection instruction. See Table 18, page 21 to Table 20, page 22. RESET The RESET instruction consists of one WRITE cycle (see Table 29, page 27). It can also be optionally preceded by the standard two WRITE
decoding cycles (writing AAh to AAAh, and 55h to 554h). The RESET instruction must be executed after: - Reading the Flash Protection Status or Flash ID - An Error condition has occurred (and the device has set the Error Flag Bit (DQ5/DQ13) to '1') during a Flash memory Program or Erase cycle. The RESET instruction immediately puts the Flash memory back into normal READ Mode. However, if there is an error condition (with the Error Flag Bit (DQ5/DQ13) set to '1') the Flash memory will return to the READ Mode in 25s after the RESET instruction is issued. The RESET instruction is ignored when it is issued during a Program or Bulk Erase cycle of the Flash memory. The RESET instruction aborts any ongoing Sector Erase cycle, and returns the Flash memory to the normal READ Mode in 25s. Reset (RESET) Pin A pulse on the Reset (RESET) pin aborts any cycle that is in progress, and resets the Flash memory to the READ Mode. When the reset occurs during a Program or Erase cycle, the Flash memory takes up to 25 s to return to the READ Mode. It is recommended that the Reset (RESET) pulse (except for Power On Reset, as described on page 74) be at least 25s so that the Flash memory is always ready for the MCU to retrieve the bootstrap instructions after the RESET cycle is complete.
SRAM The SRAM is enabled when SRAM Select (RS0) from the DPLD is High. SRAM Select (RS0) can contain up to three product terms, allowing flexible memory mapping. The SRAM can be backed up using an external battery. The external battery should be connected to the Voltage Standby (VSTBY, PE6) line. If you have an external battery connected to the PSD, the contents of the SRAM are retained in the event of a power loss. The contents of the SRAM are retained so long as the battery voltage remains at 2V or greater. If the supply voltage falls below the bat-
tery voltage, an internal power switch-over to the battery occurs. PE7 can be configured as an output that indicates when power is being drawn from the external battery. This Battery-on Indicator (VBATON, PE7) signal is High when the supply voltage falls below the battery voltage and the battery on Voltage Standby (VSTBY, PE6) is supplying power to the internal SRAM. SRAM Select (RS0), Voltage Standby (VSTBY, PE6) and Battery-on Indicator (V BATON, PE7) are all configured using PSDsoft.
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PSD4256G6V
MEMORY SELECT SIGNALS The Primary Flash Memory Sector Select (FS0FS15), Secondary Flash Memory Sector Select (CSBOOT0-CSBOOT3) and SRAM Select (RS0) signals are all outputs of the DPLD. They are defined using PSDsoft. The following rules apply to the equations for these signals: 1. Primary Flash memory and secondary Flash memory Sector Select signals must not be larger than the physical sector size. 2. Any primary Flash memory sector must not be mapped in the same memory space as another Flash memory sector. 3. A secondary Flash memory sector must not be mapped in the same memory space as another secondary Flash memory sector. 4. SRAM, I/O, and Peripheral I/O spaces must not overlap. 5. A secondary Flash memory sector may overlap a primary Flash memory sector. In case of overlap, priority is given to the secondary Flash memory sector. 6. SRAM, I/O, and Peripheral I/O spaces may overlap any other memory sector. Priority is given to the SRAM, I/O, or Peripheral I/O. Example FS0 is valid when the address is in the range of 8000h to BFFFh, CSBOOT0 is valid from 8000h to 9FFFh, and RS0 is valid from 8000h to 87FFh. Any address in the range of RS0 always accesses the SRAM. Any address in the range of CSBOOT0 greater than 87FFh (and less than 9FFFh) automatically addresses secondary Flash memory segment 0. Any address greater than 9FFFh accesses the primary Flash memory segment 0. You can see that half of the primary Flash memory segment 0 and one-fourth of secondary Flash memory segment 0 cannot be accessed in this example. Also note that an equation that defined FS1 to anywhere in the range of 8000h to BFFFh would not be valid. Figure 8 shows the priority levels for all memory components. Any component on a higher level can overlap and has priority over any component on a
lower level. Components on the same level must not overlap. Level 1 has the highest priority and level 3 has the lowest. Memory Select Configuration for MCUs with Separate Program and Data Spaces The 80C31 and compatible family of MCUs can be configured to have separate address spaces for Program memory (selected using Program Select Enable (PSEN, CNTL2)) and Data memory (selected using READ Strobe (RD, CNTL1)). Any of the memories within the PSD can reside in either space or both spaces. This is controlled through manipulation of the VM register that resides in the CSIOP space. The VM register is set using PSDsoft to have an initial value. It can subsequently be changed by the MCU so that memory mapping can be changed on-the-fly. For example, you may wish to have SRAM and primary Flash memory in the Data space at Boot-up, and secondary Flash memory in the Program space at Boot-up, and later swap the secondary Flash memory and primary Flash memory. This is easily done with the VM register by using PSDsoft to configure it for Boot-up and having the MCU change it when desired. Table 25, page 23 describes the VM Register. Figure 8. Priority Level of Memory and I/O Components
Highest Priority
Level 1 SRAM, I /O, or Peripheral I /O Level 2 Secondary Non-Volatile Memory Level 3 Primary Flash Memory Lowest Priority
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Configuration Modes for MCUs with Separate Program and Data Spaces Combined Space Modes Separate Space Modes. Program space is separated from Data space. For example, Program The Program and Data spaces are combined into Select Enable (PSEN, CNTL2) is used to access one memory space that allows the primary Flash the program code from the primary Flash memory, memory, secondary Flash memory, and SRAM to while READ Strobe (RD, CNTL1) is used to acbe accessed by either Program Select Enable cess data from the secondary Flash memory, (PSEN, CNTL2) or READ Strobe (RD, CNTL1). SRAM and I/O Port blocks. This configuration reFor example, to configure the primary Flash memquires the VM register to be set to 0Ch (see Figure ory in Combined space, Bits 2 and 4 of the VM reg9). ister are set to 1 (see Figure 10). 80C31 Memory Map Example See the Application Notes for examples. Figure 9. 8031 Memory Modules - Separate Space
DPLD
RS0 CSBOOT0-3 FS0-FS15
Primary Flash Memory
Secondary Flash Memory
SRAM
CS OE
CS OE
CS OE
PSEN RD
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Figure 10. 8031 Memory Modules - Combined Space
DPLD
RS0 CSBOOT0-3 FS0-FS15
Primary Flash Memory
Secondary Flash Memory
SRAM
RD
CS OE
CS OE
CS OE
VM REG BIT 3
VM REG BIT 4
PSEN
VM REG BIT 1
VM REG BIT 2
RD
VM REG BIT 0
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PSD4256G6V
PAGE REGISTER The 8-bit Page Register increases the addressing capability of the MCU by a factor of up to 256. The contents of the register can also be read by the MCU. The outputs of the Page Register (PGR0PGR7) are inputs to the DPLD decoder and can be included in the Sector Select (FS0-FS15, CSBOOT0-CSBOOT3), and SRAM Select (RS0) equations. If memory paging is not needed, or if not all eight page register bits are needed for memory paging, Figure 11. Page Register
RESET
these bits may be used in the CPLD for general logic. See Application Note AN1154. Table 22, page 22 and Figure 11 show the Page Register. The eight flip-flops in the register are connected to the internal data bus (D0-D7). The MCU can write to or read from the Page Register. The Page Register can be accessed at address location CSIOP + E0h.
D0 D1 D0 - D7 D2 D3 D4 D5 D6 R/ W D7
Q0 Q1 Q2 Q3 Q4 Q5
PGR0 PGR1 PGR2 PGR3 PGR4 PGR5 PGR6 DPLD AND CPLD
INTERNAL SELECTS AND LOGIC
Q6 PGR7 Q7
PAGE REGISTER
PLD
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MEMORY ID REGISTERS The 8-bit "Read only" Memory Status Registers are included in the CSIOP space. The user can determine the memory configuration of the PSD device by reading the Memory ID0 and Memory
ID1 registers. The content of the registers is defined as shown in Table 26, page 24 and Table 27, page 24.
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PSD4256G6V
PLDS The PLDs bring programmable logic functionality to the PSD. After specifying the logic for the PLDs using PSDsoft, the logic is programmed into the device and available upon Power-up. The PSD contains two PLDs: the Decode PLD (DPLD), and the Complex PLD (CPLD). The PLDs are briefly discussed in the next few paragraphs, and in more detail in the following sections. Figure 12, page 39 shows the configuration of the PLDs. The DPLD performs address decoding for internal components, such as memory, registers, and I/O ports Select signals. The CPLD can be used for logic functions, such as loadable counters and shift registers, state machines, and encoding and decoding logic. These logic functions can be constructed using the 16 Output Macrocells (OMC), 24 Input Macrocells (IMC), and the AND Array. The CPLD can also be used to generate External Chip Select (ECS0ECS2) signals. The AND Array is used to form product terms. These product terms are specified using PSDsoft. An Input Bus consisting of 82 signals is connected to the PLDs. The signals are shown in Table 32. The Turbo Bit in PSD The PLDs in the PSD4256G6V can minimize power consumption by switching to standby when inputs remain unchanged for an extended time of about 70ns. Resetting the Turbo Bit to '0' (Bit 3 of the PMMR0 register) automatically places the PLDs into standby if no inputs are changing. Turning the Turbo mode off increases propagation delays while reducing power consumption. See the section entitled "POWER MANAGEMENT", on page 70, on how to set the Turbo Bit. Additionally, five bits are available in the PMMR2 register to block MCU control signals from entering
the PLDs. This reduces power consumption and can be used only when these MCU control signals are not used in PLD logic equations. Each of the two PLDs has unique characteristics suited for its applications. They are described in the following sections. Table 32. DPLD and CPLD Inputs
Input Source MCU Address Bus(1) MCU Control Signals Reset Power-down Port A Input Macrocells Port B Input Macrocells Port C Input Macrocells Port D Inputs Port F Inputs Page Register Macrocell A Feedback Macrocell B Feedback Flash memory Program Status Bit Input Name A15-A0 CNTL0-CNTL2 RST PDN PA7-PA0 PB7-PB0 PC7-PC0 PD3-PD0 PF7-PF0 PGR7-PGR0 MCELLA.FB7-FB0 MCELLB.FB7-FB0 Ready/Busy Number of Signals 16 3 1 1 8 8 8 4 8 8 8 8 1
Note: 1. The address inputs are A19-A4 in 80C51XA mode.
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PSD4256G6V
Figure 12. PLD Diagram
8 DATA BUS
PAGE REGISTER
DECODE PLD
82
16 4 3 1 2 1
PRIMARY FLASH MEMORY SELECTS SECONDARY NON-VOLATILE MEMORY SELECTS SRAM SELECT CSIOP SELECT PERIPHERAL SELECTS JTAG SELECT
PLD INPUT BUS
16
OUTPUT MACROCELL FEEDBACK
DIRECT MACROCELL ACCESS FROM MCU DATA BUS
CPLD
82 PT ALLOC.
16 OUTPUT MACROCELL
MCELLA TO PORT A MCELLB TO PORT B
8
I/O PORTS
24 INPUT MACROCELL (PORT A,B,C)
8 8
EXTERNAL CHIP SELECTS TO PORT C or PORT F
DIRECT MACROCELL INPUT TO MCU DATA BUS 24 INPUT MACROCELL and INPUT PORTS
12
PORT D and PORT F INPUTS
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PSD4256G6V
DECODE PLD (DPLD) The DPLD, shown in Figure 13, is used for decoding the address for internal and external components. The DPLD can be used to generate the following decode signals: s 8 Sector Select (FS0-FS15) signals for the primary Flash memory (three product terms each)
s
s
1 internal SRAM Select (RS0) signal (three product terms) 1 internal CSIOP Select (PSD Configuration Register) signal 1 JTAG Select signal (enables JTAG-ISP on Port E) 2 internal Peripheral Select signals (Peripheral I/O mode).
s
s
4 Sector Select (CSBOOT0-CSBOOT3) signals for the secondary Flash memory (three product terms each)
s
Figure 13. DPLD Logic Array
3 3 3 3 (INPUTS) I /O PORTS (PORT A,B,C,F) MCELLA.FB [7:0] (FEEDBACKS) MCELLB.FB [7:0] (FEEDBACKS) PGR0 -PGR7 A[15:0] * PD[3:0] (ALE,CLKIN,CSI) PDN (APD OUTPUT) CNTRL[2:0] (READ/WRITE CONTROL SIGNALS) RESET RD_BSY (32) 3 (8) 3 (8) 3 (8) 3 (16) 3 (4) 3 (1) 3 (3) (1) 3 (1) 1 1 1 1 CSIOP PSEL0 PSEL1 JTAGSEL
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CSBOOT 0 CSBOOT 1 CSBOOT 2 CSBOOT 3 4 SECONDARY FLASH MEMORY SECTOR SELECTS
3
FS0 FS15 16 PRIMARY FLASH MEMORY SECTOR SELECTS
RS0
SRAM SELECT I/O DECODER SELECT PERIPHERAL I/O MODE SELECT
Note: 1. The address inputs are A19-A4 when in 80C51XA mode 2. Additional address lines can be brought in the PSD via Port A, B, C, D, or F.
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PSD4256G6V
COMPLEX PLD (CPLD) The CPLD can be used to implement system logic functions, such as loadable counters and shift registers, system mailboxes, handshaking protocols, state machines, and random logic. The CPLD can also be used to generate eight External Chip Select (ECS0-ECS7), routed to Port C or Port F. Although External Chip Select (ECS0-ECS7) can be produced by any Output Macrocell (OMC), these eight External Chip Select (ECS0-ECS7) on Port C or Port F do not consume any Output Macrocells (OMC). As shown in Figure 14, the CPLD has the following blocks: s 24 Input Macrocells (IMC)
s s
s
AND Array capable of generating up to 196 product terms Four I/O Ports.
s
16 Output Macrocells (OMC) Product Term Allocator
Each of the blocks are described in the sections that follow. The Input Macrocells (IMC) and Output Macrocells (OMC) are connected to the PSD internal data bus and can be directly accessed by the MCU. This enables the MCU software to load data into the Output Macrocells (OMC) or read data from both the Input and Output Macrocells (IMC and OMC). This feature allows efficient implementation of system logic and eliminates the need to connect the data bus to the AND Array as required in most standard PLD macrocell architectures.
Figure 14. Macrocell and I/O Port
PLD INPUT BUS
PRODUCT TERMS FROM OTHER MACROCELLS
MCU ADDRESS / DATA BUS
CPLD MACROCELLS
PT PRESET PRODUCT TERM ALLOCATOR MCU DATA IN
DATA LOAD CONTROL
I/O PORTS
LATCHED ADDRESS OUT DATA WR I/O PIN D Q
MCU LOAD
MUX
AND ARRAY
UP TO 10 PRODUCT TERMS
POLARITY SELECT PR DI LD PT CLOCK D/T Q
MUX
MACROCELL OUT TO MCU
CPLD OUTPUT
SELECT
COMB. /REG SELECT
PLD INPUT BUS
GLOBAL CLOCK CLOCK SELECT PT CLEAR
MUX
D/T/JK FF SELECT
CK CL
PDR
INPUT
D WR
Q
DIR REG.
PT OUTPUT ENABLE (OE) MACROCELL FEEDBACK I/O PORT INPUT
INPUT MACROCELLS
MUX
QD
MUX
PT INPUT LATCH GATE/CLOCK ALE/AS
QD G
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PSD4256G6V
Output Macrocell (OMC) Eight of the Output Macrocells (OMC) are connected to Ports A pins and are named as McellA0McellA7. The other eight Macrocells are connected to Ports B pins and are named as McellB0McellB7. The Output Macrocell (OMC) architecture is shown in Figure 15, page 44. As shown in the figure, there are native product terms available from the AND Array, and borrowed product terms available (if unused) from other Output Macrocells (OMC). The polarity of the product term is controlled by the XOR gate. The Output Macrocell (OMC) can implement either sequential logic, using the flip-flop element, or combinatorial logic.
The multiplexer selects between the sequential or combinatorial logic outputs. The multiplexer output can drive a port pin and has a feedback path to the AND Array inputs. The flip-flop in the Output Macrocell (OMC) block can be configured as a D, T, JK, or SR type in the PSDsoft program. The flip-flop's clock, preset, and clear inputs may be driven from a product term of the AND Array. Alternatively, the external CLKIN (PD1) signal can be used for the clock input to the flip-flop. The flip-flop is clocked on the rising edge of CLKIN (PD1). The preset and clear are active High inputs. Each clear input can use up to two product terms.
Table 33. Output Macrocell Port and Data Bit Assignments
Output Macrocell McellA0 McellA1 McellA2 McellA3 McellA4 McellA5 McellA6 McellA7 McellB0 McellB1 McellB2 McellB3 McellB4 McellB5 McellB6 McellB7 Port Assignment Port A0 Port A1 Port A2 Port A3 Port A4 Port A5 Port A6 Port A7 Port B0 Port B1 Port B2 Port B3 Port B4 Port B5 Port B6 Port B7 Native Product Terms 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 Maximum Borrowed Product Terms 6 6 6 6 6 6 6 6 5 5 5 5 6 6 6 6 16-bit MCU Loading or Reading(1) D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 Motorola 16-bit MCU for Loading or Reading D8 D9 D10 D11 D12 D13 D14 D15 D0 D1 D2 D3 D4 D5 D6 D7
Note: 1. D7-D0 are used for loading or reading in 8-bit mode.
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PSD4256G6V
Product Term Allocator The CPLD has a Product Term Allocator. PSDsoft, uses the Product Term Allocator to borrow and place product terms from one Macrocell to another. The following list summarizes how product terms are allocated: s McellA0-McellA7 all have three native product terms and may borrow up to six more
s
McellB0-McellB3 all have four native product terms and may borrow up to five more McellB4-McellB7 all have four native product terms and may borrow up to six more.
s
Each Macrocell may only borrow product terms from certain other Macrocells. Product terms already in use by one Macrocell are not available for another Macrocell. If an equation requires more product terms than are available to it, then "external" product terms are required, which consume other Output Macrocells (OMC). If external product terms are used, extra delay is added for the equation that required the extra product terms. This is called product term expansion. PSDsoft performs this expansion as needed. Loading and Reading the Output Macrocells (OMC) The Output Macrocells (OMC) block occupies a memory location in the MCU address space, as defined by the CSIOP (see Figure 21 to Figure 30 for examples of the basic connections between the PSD and some popular MCUs). The PSD Control input pins are labeled as to the MCU function for which they are configured. The MCU bus interface is specified using the PSDsoft Express Configuration. The flip-flops in each of the 16 Output Macrocells (OMC) can be loaded from the data bus by a MCU. Loading the Output Macrocells (OMC) with data from the MCU takes priority over internal functions. As such, the preset, clear, and clock in-
puts to the flip-flop can be overridden by the MCU. The ability to load the flip-flops and read them back is useful in such applications as loadable counters and shift registers, mailboxes, and handshaking protocols. Data is loaded to the Output Macrocells (OMC) on the trailing edge of WRITE Strobe (WR/WRL, CNTL0). The OMC Mask Register There is one Mask Register for each of the two groups of eight Output Macrocells (OMC). The Mask Registers can be used to block the loading of data to individual Output Macrocells (OMC). The default value for the Mask Registers is 00h, which allows loading of the Output Macrocells (OMC). When a given bit in a Mask Register is set to a 1, the MCU is blocked from writing to the associated Output Macrocells (OMC). For example, suppose McellA0-McellA3 are being used for a state machine. You would not want a MCU WRITE to McellA to overwrite the state machine registers. Therefore, you would want to load the Mask Register for McellA (Mask Macrocell A) with the value 0Fh. The Output Enable of the OMC The Output Macrocells (OMC) can be connected to an I/O port pin as a PLD output. The output enable of each port pin driver is controlled by a single product term from the AND Array, ORed with the Direction Register output. The pin is enabled upon Power-up if no output enable equation is defined and if the pin is declared as a PLD output in PSDsoft. If the Output Macrocell (OMC) output is declared as an internal node and not as a port pin output in the PSDabel file, then the port pin can be used for other I/O functions. The internal node feedback can be routed as an input to the AND Array.
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Figure 15. CPLD Output Macrocell
MASK REG. MACROCELL CS RD
INTERNAL DATA BUS
PT ALLOCATOR
WR DIRECTION REGISTER ENABLE (.OE) PRESET(.PR) COMB/REG SELECT
AND ARRAY
PT PT DIN PR
PLD INPUT BUS
MUX PT LD POLARITY SELECT CLEAR (.RE) PT CLK CLKIN MUX IN CLR PROGRAMMABLE FF (D / T/JK /SR) PORT DRIVER Q
I/O PIN
FEEDBACK (.FB) PORT INPUT INPUT MACROCELL
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PSD4256G6V
Input Macrocells (IMC) The CPLD has 24 Input Macrocells (IMC), one for each pin on Ports A, B, and C. The architecture of the Input Macrocells (IMC) is shown in Figure 16. The Input Macrocells (IMC) are individually configurable, and can be used as a latch, register, or to pass incoming Port signals prior to driving them onto the PLD input bus. The outputs of the Input Macrocells (IMC) can be read by the MCU through the internal data bus. The enable for the latch and clock for the register are driven by a multiplexer whose inputs are a product term from the CPLD AND Array or the MCU Address Strobe (ALE/AS). Each product term output is used to latch or clock four Input Macrocells (IMC). Port inputs 3-0 can be controlled by one product term and 7-4 by another. Configurations for the Input Macrocells (IMC) are specified by PSDsoft (see Application Note AN1171). Outputs of the Input Macrocells (IMC) can be read by the MCU via the IMC buffer. See Figure 21, page 51 to Figure 26, page 57 for examples of the basic connections between the PSD and some popular MCUs. The PSD Control input pins are labeled as to the MCU function for which Figure 16. Input Macrocell
INTERNAL DATA BUS
they are configured. The MCU bus interface is specified using the "I/O Ports", on page 16. Input Macrocells (IMC) can use Address Strobe (ALE/AS, PD0) to latch address bits higher than A15. Any latched addresses are routed to the PLDs as inputs. Input Macrocells (IMC) are particularly useful with handshaking communication applications where two processors pass data back and forth through a common mailbox. Figure 18, page 46 shows a typical configuration where the Master MCU writes to the Port A Data Out Register. This, in turn, can be read by the Slave MCU via the activation of the "Slave-READ" output enable product term. The Slave can also write to the Port A Input Macrocells (IMC) and the Master can then read the Input Macrocells (IMC) directly. Note that the "Slave-READ" and "Slave-Wr" signals are product terms that are derived from the Slave MCU inputs READ Strobe (RD, CNTL1), WRITE Strobe (WR/WRL, CNTL0), and Slave_CS.
INPUT MACROCELL _ RD ENABLE ( .OE ) OUTPUT MACROCELLS A AND MACROCELLS B
DIRECTION REGISTER
PT AND ARRAY
PLD INPUT BUS
I/O PIN PT
PORT DRIVER
MUX
Q
D MUX
PT ALE/AS
D FF FEEDBACK Q D G LATCH INPUT MACROCELL
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PSD4256G6V
External Chip Select The CPLD also provides eight External Chip Select (ECS0-ECS7) outputs that can be used to select external devices. Each External Chip Select (ECS0-ECS7) consists of one product term that can be configured active High or Low. Figure 17. External Chip Select Signal
The output enable of the pin is controlled by either the output enable product term or the Direction Register. (See Figure 17.)
Port C or Port F CPLD AND ARRAY
PLD INPUT BUS
ENABLE (.OE) PT
DIRECTION REGISTER
ECS PT
ECS To Port C or F
PORT PIN
POLARITY BIT
AI04927
Figure 18. Handshaking Communication Using Input Macrocells
PSD
SLAVE - CS RD WR SLAVE - READ PORT A DATA OUT REGISTER MCU- RD MCU- WR MASTER MCU D [ 7:0] PORT A INPUT MACROCELL Q MCU - RD D CPLD MCU - WR D [ 7:0] D Q PORT A
SLAVE MCU
SLAVE - WR
AI02877C
46/100
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
PSD4256G6V
MCU BUS INTERFACE The "no-glue logic" MCU Bus Interface block can be directly connected to most popular 8-bit and 16bit MCUs and their control signals. Key MCUs, Table 34. 16-bit MCUs and Their Control Signals
MCU 68302, 68306, MMC2001 68330, 68331, 68332, 68340 68LC302, MMC2001 68HC16 68HC912 68HC812 3 80196 80196SP 80186 80C161, 80C164-80C167 80C51XA H8/300 CNTL0 R/W R/W WEL R/W R/W R/W WR WRL WR WR WRL WRL CNTL1 LDS DS OE DS E E RD RD RD RD RD RD CNTL2 UDS SIZ0 -- SIZ0 LSTRB LSTRB BHE (Note 1) BHE BHE PSEN (Note 1) PD3 (Note 1) (Note 1) WEH (Note 1) DBE (Note 1) (Note 1) WRH (Note 1) (Note 1) WRH WRH PD02 AS AS AS AS E (Note 1) ALE ALE ALE ALE ALE AS ADIO0 -- A0 -- A0 A0 A0 A0 A0 A0 A0 A4/D0 A0 PF3-PF0 (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) A3-A1 --
with their bus types and control signals, are shown in Table 34. The MCU interface type is specified using the PSDsoft.
Note: 1. Unused CNTL2 pin can be configured as CPLD input. Other unused pins (PD3-PD0, PF3-PF0) can be configured for other I/O functions. 2. ALE/AS input is optional for MCUs with a non-multiplexed bus. 3. This configuration is for MC68HC812A4_EC at 5MHz, 3V only.
47/100
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PSD4256G6V
PSD Interface to a Multiplexed Bus Figure 19 shows an example of a system using an MCU with a multiplexed bus and a PSD4256G6V. The ADIO port on the PSD is connected directly to the MCU address/data bus. Address Strobe (ALE/ AS, PD0) latches the address signals internally. Latched addresses can be brought out to Port E, F
or G. The PSD drives the ADIO data bus only when one of its internal resources is accessed and READ Strobe (RD, CNTL1) is active. Should the system address bus exceed sixteen bits, Ports A, B, C, or F may be used as additional address inputs.
Figure 19. An Example of a Typical Multiplexed Bus Interface
MCU
AD [ 7:0]
PSD
PORT F A [ 7: 0] (OPTIONAL)
AD[15:8]1
or A[15:8]
ADIO PORT
PORT G WR RD BHE WR (CNTRL0) RD (CNTRL1) BHE (CNTRL2) RST ALE ALE (PD0) PORT D RESET PORT A
A [ 15: 8] (OPTIONAL)
A [ 23:16] (OPTIONAL)
AI04928B
Note: 1. AD[15:8] is for 16-bit MCU
48/100
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PSD4256G6V
PSD Interface to a Non-Multiplexed, 16-bit Bus Figure 20 shows an example of a system using an MCU with a 16-bit, non-multiplexed bus and a PSD4256G6V. The address bus is connected to the ADIO Port, and the data bus is connected to Ports F and G. Ports F and G are in tri-state mode
when the PSD is not accessed by the MCU. Should the system address bus exceed sixteen bit, Ports A, B, or C may be used for additional address inputs.
Figure 20. An Example of a Typical Non-Multiplexed Bus Interface
MCU
D [ 15:0]
PSD
PORT F D [ 7:0]
ADIO PORT A [ 15:0]
PORT G WR RD BHE WR (CNTRL0) RD (CNTRL1) BHE (CNTRL2) RST PORT A
D[15:8]1
A [ 23:16] (OPTIONAL)
ALE
ALE (PD0) PORT D
RESET
AI04929B
Note: 1. D[15:8] is for 16-bit MCU
49/100
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PSD4256G6V
Data Byte Enable Reference for a 16-bit Bus MCUs have different data byte orientations. Table 35 to Table 38 show how the PSD4256G6V interprets byte/word operations in different bus WRITE configurations. Even-byte refers to locations with address A0 equal to 0, and odd byte as locations with A0 equal to 1. Table 35. 16-Bit Data Bus with BHE
BHE 0 0 1 A0 0 1 0 D15-D8 Odd Byte Odd Byte -- D7-D0 Even Byte -- Even Byte
16-bit MCU Bus Interface Examples Figure 21, page 51 to Figure 26, page 57 show examples of the basic connections between the PSD4256G6V and some popular MCUs. The PSD4256G6V Control input pins are labeled as to the MCU function for which they are configured. The MCU bus interface is specified using PSDsoft. The Voltage Standby (VSTBY, PE6) line should be held at Ground if not in use. Table 36. 16-Bit Data Bus with WRH and WRL
WRH 0 0 1 WRL 0 1 0 D15-D8 Odd Byte Odd Byte -- D7-D0 Even Byte -- Even Byte
Table 37. 16-Bit Data Bus with SIZ0, A0 (Motorola MCU)
SIZ0 0 1 1 A0 0 0 1 D15-D8 Even Byte Even Byte -- D7-D0 Odd Byte -- Odd Byte
Table 38. 16-Bit Data Bus with LDS, UDS (Motorola MCU)
WRH 0 1 0 WRL 0 0 1 D15-D8 Even Byte Even Byte -- D7-D0 Odd Byte -- Odd Byte
50/100
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
PSD4256G6V
80C196 and 80C186 In Figure 21, the Intel 80C196 MCU, which has a 16-bit multiplexed address/data bus, is shown connected to a PSD4256G6V. The READ Strobe (RD, CNTL1), and WRITE Strobe (WR/WRL, CNTL0) signals are connected to the CNTL pins. When BHE is not used, the PSD can be configured to receive WRL and WRITE Enable High-byte Figure 21. Interfacing the PSD with an 80C196
A19-A16 AD15-AD0 VCC
(WRH/DBE, PD3) from the MCU. Higher address inputs (A16-A19) can be routed to Ports A, B, or C as input to the PLD. The AMD 80186 family has the same bus connection to the PSD as the 80C196.
A[ 19:16] AD[ 15:0 ]
80C196NT
19 X1 P3.0/AD0 P3.1/AD1 P3.2/AD2 P3.3/AD3 P3.4/AD4 P3.5/AD5 P3.6/AD6 P3.7/AD7 P4.0/AD8 P4.1/AD9 P4.2/AD10 P4.3/AD11 P4.4/AD12 P4.5/AD13 P4.6/AD14 P4.7/AD15 EP.0/A16 EP.1/A17 EP.2/A18 EP.3/A19 WR/WRL/P5.2 RD/P5.3 BHE/WRH/P5.5 ALE/ADV/P5.0 3 4 5 6 7 10 11 12 13 14 15 16 17 18 19 20 14 13 12 11 9 7 8 4 A16 A17 A18 A19 WR RD BHE ALE 59 60 40 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 3 4 5 6 7 10 11 12 13 14 15 16 17 18 19 20
PSD
ADIO0 ADIO1 ADIO2 ADIO3 ADIO4 ADIO5 ADIO6 ADIO7 ADIO8 ADIO9 ADIO10 ADIO11 ADIO12 ADIO13 ADIO14 ADIO15
9 VCC
29 VCC
69 VCC PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 31 32 33 34 35 36 37 38
18 32 49 6 48 44 45 46 47 58 59 60 61 62 63 64 65
X2 NMI VREF VPP ANGND ACH4/P0.4/PMD.0 ACH5/P0.5/PMD.1 ACH6/P0.6/PMD.2 ACH7/P0.7/PMD.3
PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7
21 22 23 24 25 26 27 28 51 52 53 54 55 56 57 58 61 62 63 64 65 66 67 68 41 42 43 44 45 46 47 48 A16 A17 A18 A19
P6.0/EPA8 P6.1/EPA9 P6.2/T1CLK P6.3/T1DIR P6.4/SC0 P6.5/SD0 P6.6/SC1 P6.7/SD1
CNTL0 (WR) CNTL1 (RD) CNTL2 (BHE) PD0 (ALE) PD1 (CLKIN) PD2 (CSI) PD3 (WRH)
36 37 38 39 40 41 42 43 57 56 55 54 53 52 51 50
P2.0/TX/PVR P2.1/RXD/PALE P2.2/EXINT/PROG P2.3/INTB P2.4/INTINTOUT P2.5/HLD P2.6/HLDA/CPVER P2.7/CLKOUT/PAC
EA
33
79 80 1 2
31 RESET
RESET
39
RESET
P1.0/EPA0/T2CLK P1.1/EPA1 P1.2/EPA2/T2DIR P1.3/EPA3 BUSWIDTH/P5.7 P1.4/EPA4 P1.5/EPA5 INST/P5.1 P1.6/EPA6 SLPINT/P5.4 P1.7/EPA7
READY/P5.6
2
10 3 1
71 72 73 74 75 76 77 78
PE0 (TMS) PE1 (TCK/ST) PE2 (TDI) PE3 (TDO) PE4 (TSTAT/RDY) PE5 (TERR) PE6 (VSTBY) PE7 (VBATON) GND GND GND GND GND 8 30 49 50 70
RESET
AI04930
51/100
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
PSD4256G6V
MC683xx and MC68HC16 Figure 22 shows a MC68331 with a 16-bit nonmultiplexed data bus and 24-bit address bus. The data bus from the MC68331 is connected to Port F (D0-D7) and Port G (D8-D15). The SIZ0 and A0 inputs determine the high/low byte selection. The R/ Figure 22. Interfacing the PSD with an MC68331
D[15:0] D[15:0] A[23:0] VCC_BAR A[23:0]
W, DS and SIZ0 signals are connected to the CNTL0-CNTL2 pins. The MC68HC16, and other members of the MC683xx family, has the same bus connection to the PSD as the MC68331 shown in Figure 22.
29 Vcc
PSD MC68331 D0 D1 D2 D3 D4 D5 D6 D7 111 110 109 108 105 104 103 102 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19_CS6/ A20_CS7/ A21_CS8/ A22_CS9/ A23_CS10/ 90 20 21 22 23 24 25 26 27 30 31 32 33 35 36 37 38 41 42 121 122 123 124 125 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 3 4 5 6 7 10 11 12 13 14 15 16 17 18 19 20 ADIO0 ADIO1 ADIO2 ADIO3 ADIO4 ADIO5 ADIO6 ADIO7 ADIO8 ADIO9 ADIO10 ADIO11 ADIO12 ADIO13 ADIO14 ADIO15
Vcc
9
Vcc
69
PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7
31 32 33 34 35 36 37 38 21 22 23 24 25 26 27 28 51 52 53 54 55 56 57 58 61 62 63 64 65 66 67 68 41 42 43 44 45 46 47 48
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
D8 100 D9 99 D10 98 D11 97 D12 94 D13 93 D14 92 D15 91
R/W\ DS\ SIZ0 AS
59 60 40 79 80 1 2 39 71 72 73 74 75 76 77 78
CNTL0(R/W) CNTL1(DS) CNTL2 (SIZ0) PD0 (AS) PD1 (CLKIN) PD2 (CSI) PD3 RESET PE0 (TMS) PE1 (TCK/ST) PE2 (TDI) PE3 (TDO) PE4 (TSTAT/RDY) PE5 (TERR) PE6 (VSTBY) PE7 (VBATON)
89 88 77 76 75 74 73 72 71
DSACK0 DSACK1 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7
79 R_W 85 DS 81 SIZ0 AS 82
RESET
68
RESET\
A16 A17 A18 A19
SIZ1 CLKOUT CSBOOT/ BR_CS0/ BG_CS1/ BGACK_CS2/ FC0_CS3/ FC1_CS4/ FC2_CS5/ RESET\
80 66 112 113 114 115 118 119 120
8 30 49 50 70
GND GND GND GND GND
AI04951b
52/100
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
PSD4256G6V
80C51XA The Philips 80C51XA MCU has a 16-bit multiplexed bus with burst cycles. Address bits (A3-A1) are not multiplexed, while (A19-A4) are multiplexed with data bits (D15-D0). The PSD4256G6V supports the 80C51XA burst mode. The WRH signal is connected to PD3, and WHL is connected to CNTL0. The RD and PSEN signals are connected to the CNTL1 and CNTL2 pins. Figure 23 shows the schematic diagram.
The 80C51XA improves bus throughput and performance by issuing burst cycles to retrieve codes from memory. In burst cycles, address A19-A4 are latched internally by the PSD, while the 80C51XA drives the A3-A1 signals to retrieve sequentially up to 16 bytes of code. The PSD access time is then measured from address A3-A1 valid to data in valid. The PSD bus timing requirement in a burst cycle is identical to the normal bus cycle, except the address setup and hold time with respect to Address Strobe (ALE/AS, PD0) is not required.
Figure 23. Interfacing the PSD with an 80C51XA-G3
D[15:0]
D[15:0] A[3:1] VCC_BAR
A[3:1]
PSD XA-G3 21 U3 CRYSTAL 20 11 13 6 7 9 8 16 XTAL1 A4D0 A5D1 A6D2 A7D3 A8D4 A9D5 A10D6 A11D7 A12D8 A13D9 A14D10 A15D11 A16D12 A17D13 A18D14 A19D15 A3 A2 A1 A0/WRH WRL RD PSEN 43 42 41 40 39 38 37 36 24 25 26 27 28 29 30 31 5 4 3 2 18 19 32 A3 A2 A1 WRH\ WRL\ RD\ PSEN\ 3 A4D0 4 A5D1 A6D2 5 6 A7D3 A8D4 7 A9D5 10 A10D6 11 A11D7 12 A12D8 13 A13D9 14 A14D10 15 A15D11 16 A16D12 17 A17D13 18 A18D14 19 A19D15 20 ADIO0 ADIO1 ADIO2 ADIO3 ADIO4 ADIO5 ADIO6 ADIO7
Vcc
Vcc
29
9
Vcc
69
XTAL2 RXD0 TXD0 RXD1 TXD1 T2EX T2 T0
PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7
31 32 33 34 35 36 37 38 21 22 23 24 25 26 27 28 51 52 53 54 55 56 57 58 61 62 63 64 65 66 67 68 41 42 43 44 45 46 47 48
A1 A2 A3
ADIO8 ADIO9 ADIO10 ADIO11 ADIO12 ADIO13 ADIO14 ADIO15
RESET\
10 14 15 35 17
RST INT0 INT1 EA/WAIT
59 60 40
CNTL0(WR) CNTL1(RD) CNTL2(PSEN)
ALE BUSW
33
ALE
VCC_BAR RESET\
79 80 1 2
PD0 (ALE) PD1 (CLKIN) PD2 (CSI) PD3 (WRH) RESET PE0 (TMS) PE1 (TCK/ST) PE2 (TDI) PE3 (TDO) PE4 (TSTAT/RDY) PE5 (TERR) PE6 (VSTBY) PE7 (VBATON)
39 71 72 73 74 75 76 77 78
8 30 49 50 70
GND GND GND GND GND
AI04952b
53/100
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
PSD4256G6V
H8/300 Figure 24 shows an Hitachi H8/2350 with a 16-bit non-multiplexed data bus, and a 24-bit address bus. The H8 data bus is connected to Port F (D0D7) and Port G (D8-D15).
The WRH signal is connected to PD3, and WHL is connected to CNTL0. The RD signal is connected to CNTL1. The connection to the Address Strobe (AS) signal is optional, and is required if the addresses are to be latched.
Figure 24. Interfacing the PSD with an H83/2350
D[15:0] D[15:0] A[23:0] A[23:0] VCC_BAR
29 Vcc
H8S/2655 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 34 35 36 37 39 40 41 42 43 44 45 46 48 49 50 51 78 U3 CRYSTAL 77 XTAL 2 3 4 5 7 8 9 10 11 12 13 14 16 17 18 19 20 21 22 23 25 26 27 28 85 83 82 84 73 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 3 4 5 6 7 10 11 12 13 14 15 16 17 18 19 20
PSD PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 PC6/A6 PC7/A7 PB0/A8 PB1/A9 PB2/A10 PB3/A11 PB4/A12 PB5/A13 PB6/A14 PB7/A15 PA0/A16 PA1/A17 PA2/A18 PA3/A19 PA4/A20/IRQ4 PA5/A21/IRQ5 PA6/A22/IRQ6 PA7/A23/IRQ7 LWR RD AS HWR RESET ADIO0 ADIO1 ADIO2 ADIO3 ADIO4 ADIO5 ADIO6 ADIO7 ADIO8 ADIO9 ADIO10 ADIO11 ADIO12 ADIO13 ADIO14 ADIO15
Vcc
9
Vcc
69
PE0/D0 PE0/D1 PE0/D2 PE0/D3 PE0/D4 PE0/D5 PE0/D6 PE0/D7 PD0/D8 PD1/D9 PD2/D10 PD3/D11 PD4/D12 PD5/D13 PD6/D14 PD7/D15 EXTAL
PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7
31 32 33 34 35 36 37 38 21 22 23 24 25 26 27 28 51 52 53 54 55 56 57 58 61 62 63 64 65 66 67 68 41 42 43 44 45 46 47 48
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
WRL\ RD\
59 60 40
CNTL0(WRL) CNTL1(RD) CNTL2 PD0 (AS) PD1 (CLKIN) PD2 (CSI) PD3 (WRH) RESET PE0 (TMS) PE1 (TCK/ST) PE2 (TDI) PE3 (TDO) PE4 (TSTAT/RDY) PE5 (TERR) PE6 (VSTBY) PE7 (VBATON)
29 30 31 32 55 53 57 56 54 58 90 89 91 88 87 86 74 71 70 69 68 67 66 65 64 60 61 62 63 113 114 115 80
CS7/IRQ3 CS6/IRQ2 IRQ1 IRQ0 RXD0 TXD0 SCK0 RXD1 TXD1 SCK1 RXD2 TXD2 SCK2 PF0/BREQ PF1/BACK PF2/LCAS/WAIT/B NMI PO0/TIOCA3 PO1/TIOCB3 PO2/TIOCC3/TMRI PO3/TIOCD3/TMCI PO4/TIOCA4/TMRI PO5/TIOCB4/TMRC PO6/TIOCA5/TMRO PO7/TIOCB5/TMRO DREQ/CS4 TEND0/CS5 DREQ1 TEND1 MOD0 MOD1 MOD2 PF0/PHI0
AS WRH\ RESET\
79 80 1 2 39 71 72 73 74 75 76 77 78
WDTOVF STBY PO8/TIOCA0/DACK PO9/TIOCB0/DACK PO10/TIOCC0/TCL PO11/TIOCD0/TCL PO12/TIOCA1 PO13/TIOCB1/TCL PO14/TIOCA2 PO15/TIOCB2/TCL AN0 AN1 AN2 AN3 AN4 AN5 AN6/DA0 AN7/DA1 ADTRG PG0/CAS/OE PG1/CS3 PG2/CS2 PG3/CS1 PG4/CS0
72 75 112 111 110 109 108 107 106 105 95 96 97 98 99 100 101 102 92 116 117 118 119 120
A16 A17 A18 A19
RESET\
8 30 49 50 70
GND GND GND GND GND
AI04953b
54/100
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
PSD4256G6V
MMC2001 The Motorola MCORE MMC2001 MCU has a MOD input pin that selects internal or external boot ROM. The PSD can be configured as the external flash boot ROM or as extension to the internal ROM (see Figure 25, page 56). The MMC2001 has a 16-bit external data bus and 20 address lines with external chip select signals. The Chip Select Control Registers allow the user to customize the bus interface and timing to fit the individual system requirement. A typical interface configuration to the PSD is shown in Figure 25, page 56. The MMC2001's R/W signal is connected to the CNTL0 pin, while EB0 and EB1 (enable byte-0 and enable byte-1) are connected to the CNTL1 (UDS) and CNTL2 (LDS) pins. The WEN bit in the Chip Select Control Register should be set to 1 to terminate the EB0-EB1 earlier to provide the write data hold time for the PSD. The WSC and WWS bits in the Control Register are set
to wait states that meet the PSD access time requirement. Another option is to configure the EB0 and EB1 as WRL and WRH signals. In this case, the PSD control setting will be: OE, WRL, WRH where OE is the READ signal for the MMC2001. C16x Family The PSD supports Infineon's C16X family of MCUs (C161-C167) in both the multiplexed and non-multiplexed bus configuration. In Figure 26, page 57, the C167CR is shown connected to the PSD in a multiplexed bus configuration. The control signals from the MCU are WR, RD, BHE and ALE, and are routed to the corresponding PSD pins. The C167 has another control signal setting (RD, WRL, WRH, ALE) which is also supported by the PSD.
55/100
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
PSD4256G6V
Figure 25. Interfacing the PSD with an MMC2001
A[19:16] A[19:16] AD[15:0] VCC_BAR VCC_BAR ADIO[15:0]
144 136 126 109 93
Vcc
Vcc
138 U3 CRYSTAL 137 65 66 67 68 69 70 73 74 75 76 77 78 80 81 27 28 29 30 31 32 33 34 35 36 39 40 41 42 43 44 1 2 3 4 5 6 7 8 19 20 21 22 23 24 25 26 9 10 11 12 13 14 15 16 37 97
XTAL1
XTAL2 P3.0/T0IN P3.1/T6OUT P3.2/CAPIN P3.3/T3OUT P3.4/T3EUD P3.5/T4IN P3.6/T3IN P3.7/T2IN P3.8/MRST P3.9/MTSR P3.10/TXD0 P3.11/RXD0 P3.13/SCLK P3.15/CLKOUT P5.0/AN0 P5.1/AN1 P5.2/AN2 P5.3/AN3 P5.4/AN4 P5.5/AN5 P5.6/AN6 P5.7/AN7 P5.8/AN8 P5.9/AN9 P5.10/AN10/T6UED P5.11/AN11/T5UED P5.12/AN12/T6IN P5.13/AN13/T5IN P5.14/AN14/T4UED P5.15/AN15/T2UED P6.0/!CS0 P6.1/!CS1 P6.2/!CS2 P6.3/!CS3 P6.4/!CS4 P6.5/!HOLD P6.6/!HLDA P6.7/!BREQ P7.0/POUT0 P7.1/POUT1 P7.2/POUT2 P7.3/POUT3 P7.4/CC28IO P7.5/CC29IO P7.6/CC30IO P7.7/CC31IO P8.0/CC16IO P8.1/CC17IO P8.2/CC18IO P8.3/CC19IO P8.4/CC20IO P8.5/CC21IO P8.6/CC22IO P8.7/CC23IO Vref READY
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15
100 101 102 103 104 105 106 107 108 111 112 113 114 115 116 117 85 86 87 88 89 90 91 92 96 95 79 98 99 135 134 133 132 131 130 129 128 125 124 123 122 121 120 119 118 47 48 49 50 51 52 53 54 57 58 59 60 61 62 63 64 140 141 142 A16 A17 A18 A19
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15
3 4 5 6 7 10 11 12 13 14 15 16 17 18 19 20
Vcc
Infineon C167CR
82 72 56 46 17
9
PSD
29
69
ADIO0 ADIO1 ADIO2 ADIO3 ADIO4 ADIO5 ADIO6 ADIO7 ADIO8 ADIO9 ADIO10 ADIO11 ADIO12 ADIO13 ADIO14 ADIO15
PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7
31 32 33 34 35 36 37 38 21 22 23 24 25 26 27 28 51 52 53 54 55 56 57 58 61 62 63 64 65 66 67 68 41 42 43 44 45 46 47 48 A16 A17 A18 A19
Vcc Vcc Vcc Vcc Vcc
Vcc Vcc Vcc Vcc Vcc
P4.0/A16 A17 A18 A19 A20 A21 A22 P4.7/A23 WR/WRL RD P3.12/BHE/WRH ALE EA P1H7 P1H6 P1H5 P1H4 P1H3 P1H2 P1H1 P1H0 P1L7 P1L6 P1L5 P1L4 P1L3 P1L2 P1L1 P1L0 P2.0/CC0IO P2.1/CC1IO P2.2/CC2IO P2.3/CC3IO P2.4/CC4IO P2.5/CC5IO P2.6/CC6IO P2.7/CC7IO P2.8/CC8IO/EX0IN P2.9/CC9IO/EX1IN P2.10/CC10IO/EX2IN P2.11/CC11IO/EX3IN P2.12/CC12IO/EX4IN P2.13/CC13IO/EX5IN P2.14/CC14IO/EX6IN P2.15/CC15IO/EX7IN RSTIN RSTOUT NMI
WR\ RD\ BHE\ ALE
59 60 40 79 80 1 2 39 71 72 73 74 75 76 77 78
CNTL0(WR) CNTL1(RD) CNTL2(BHE) PD0 (ALE) PD1 (CLKIN) PD2 (CSI) PD3 (WRH) RESET PE0 (TMS) PE1 (TCK/ST) PE2 (TDI) PE3 (TDO) PE4 (TSTAT/RDY) PE5 (TERR) PE6 (VSTBY) PE7 (VBATON)
RESET\
143 139 127 110 94
83 71 55 45 18
RESET\
38
Agnd
Vss Vss Vss Vss Vss
Vss Vss Vss Vss Vss
8 30 49 50 70
GND GND GND GND GND
AI04954b
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PSD4256G6V
Figure 26. Interfacing the PSD with a C167CR
A19-A16 AD15-AD0 Vcc 144136129109 93 82 72 56 46 17 VccVccVccVccVccVccVccVccVccVcc 138 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 P4.0/A16 P4.1/A17 P4.2/A18 P4.3/A19 P4.4/A20 P4.5/A21 P4.6/A22 P4.7/A23 100 101 102 103 104 105 106 107 108 111 112 113 114 115 116 117 85 86 87 88 89 90 91 92 96 95 79 98 99 135 134 133 132 131 130 129 128 125 124 123 122 121 120 119 118 47 48 49 50 51 52 53 54 57 58 59 60 61 62 63 64 140 RSTIN RSTOUT 141 142 A16 A17 A18 A19 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 3 4 5 6 7 10 11 12 13 14 15 16 17 18 19 20 VCC
A[ 19:16] AD[ 15:0 ]
PSD
ADIO0 ADIO1 ADIO2 ADIO3 ADIO4 ADIO5 ADIO6 ADIO7 ADIO8 ADIO9 ADIO10 ADIO11 ADIO12 ADIO13 ADIO14 ADIO15
9 VCC
29 VCC
69 VCC PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 31 32 33 34 35 36 37 38
XTAL1
C167CR
137 65 66 67 68 69 70 73 74 75 76 77 78 79 80 81 27 28 29 30 31 32 33 34 35 36 39 40 41 42 43 44 1 2 3 4 5 6 7 8 19 20 21 22 23 24 25 26 9 10 11 12 13 14 15 16 37 97 XTAL2 P3.0/T0IN P3.1/T6OUT P3.2/CAPIN P3.3/T3OUT P3.4/T3UED P3.5/T4IN P3.6/T3IN P3.7/T2IN P3.8/MRST P3.9/MTSR P3.10/TXD0 P3.11/RXD0 P3.12 P3.13/SCLK P3.15/CLKOUT
PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7
21 22 23 24 25 26 27 28 51 52 53 54 55 56 57 58 61 62 63 64 65 66 67 68 41 42 43 44 45 46 47 48 A16 A17 A18 A19
P5.0/AN0 WR/WRL P5.1/AN1 P5.2/AN2 RD P5.3/AN3 P312/BHE/WRH P5.4/AN4 P5.5/AN5 ALE P5.6/AN6 P5.7/AN7 EA P5.8/AN8 P5.9/AN9 P1H7 P5.10/AN10/T6UED P1H6 P5.11/AN11/T5UED P1H5 P5.12/AN12/T6IN P1H4 P5.13/AN13 P1H3 P5.14/AN14/T4UED P1H2 P5.15/AN15/T2UED P1H1 P1H0 P6.0/!CS0 P1L7 P6.1/!CS1 P1L6 P6.2/!CS2 P1L5 P6.3/!CS3 P1L4 P6.4/!CS4 P1L3 P6.5/!HOLD P1L2 P1L1 P6.6/!HLDA P1L0 P6.7/!BREQ P7.0/POUT0 P7.1/POUT1 P7.2/POUT2 P7.3/POUT3 P7.4/CC28IO P7.5/CC29IO P7.6/CC30IO P7.7/CC31IO P8.0/CC16IO P8.1/CC17IO P8.2/CC18IO P8.3/CC19IO P8.4/CC20IO P8.5/CC21IO P8.6/CC22IO P8.7/CC23IO Vref READY P2.0/CC0IO P2.1/CC1IO P2.2/CC2IO P2.3/CC3IO P2.4/CC4IO P2.5/CC5IO P2.6/CC6IO P2.7/CC7IO P2.8/CC8IO/EX0IN P2.9/CC9IO/EX1IN P2.10/CC10IO/EX2IN P2.11/CC11IO/EX3IN P2.12/CC12IO/EX4IN P2.13/CC13IO/EX5IN P2.14/CC14IO/EX6IN P2.15/CC15IO/EX7IN
WR RD BHE ALE
59 60 40 79 80 1 2
CNTL0 (WR) CNTL1 (RD) CNTL2 (BHE) PD0 (ALE) PD1 (CLKIN) PD2 (CSI) PD3 (WRH) RESET PE0 (TMS) PE1 (TCK/ST) PE2 (TDI) PE3 (TDO) PE4 (TSTAT/RDY) PE5 (TERR) PE6 (VSTBY) PE7 (VBATON) GND GND GND GND GND 8 30 49 50 70
RESET
39 71 72 73 74 75 76 77 78
NMI AGND VssVssVssVssVssVssVssVssVssVss 143139127110 94 83 71 55 45 18 38
RESET
AI04955
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PSD4256G6V
I/O PORTS There are seven programmable I/O ports: Ports A, B, C, D, E, F and G. Each port pin is individually user configurable, thus allowing multiple functions per port. The ports are configured using PSDsoft or by the MCU writing to on-chip registers in the CSIOP space. The topics discussed in this section are: s General Port architecture
s s s s
Port operating modes Port Configuration Registers (PCR) Port Data Registers Individual Port functionality.
General Port Architecture The general architecture of the I/O Port block is shown in Figure 27, page 59. Individual Port architectures are shown in Figure 29, page 66 to Figure 31, page 69. In general, once the purpose for a port pin has been defined, that pin is no longer available for other purposes. Exceptions are noted. As shown in Figure 27, page 59, the ports contain an output multiplexer whose select signals are driven by the configuration bits in the Control Registers (Ports E, F and G only) and PSDsoft Configuration. Inputs to the multiplexer include the following: s Output data from the Data Out register
s s s
Latched address outputs CPLD Macrocell output External Chip Select from the CPLD.
The Port Data Buffer (PDB) is a tri-state buffer that allows only one source at a time to be read. The Port Data Buffer (PDB) is connected to the Internal Data Bus for feedback and can be read by the MCU. The Data Out and Macrocell outputs, Direction Register and Control Register, and port pin input are all connected to the Port Data Buffer (PDB).
The Port pin's tri-state output driver enable is controlled by a two input OR gate whose inputs come from the CPLD AND Array enable product term and the Direction Register. If the enable product term of any of the Array outputs are not defined and that port pin is not defined as a CPLD output in the PSDabel file, the Direction Register has sole control of the buffer that drives the port pin. The contents of these registers can be altered by the MCU. The Port Data Buffer (PDB) feedback path allows the MCU to check the contents of the registers. Ports A, B, and C have embedded Input Macrocells (IMC). The Input Macrocells (IMC) can be configured as latches, registers, or direct inputs to the PLDs. The latches and registers are clocked by Address Strobe (ALE/AS, PD0) or a product term from the PLD AND Array. The outputs from the Input Macrocells (IMC) drive the PLD input bus and can be read by the MCU. See the section entitled "Input Macrocells (IMC)", on page 45. Port Operating Modes The I/O Ports have several modes of operation. Some modes can be defined using PSDsoft, some by the MCU writing to the registers in CSIOP space, and some by both. The modes that can only be defined using PSDsoft must be programmed into the device and cannot be changed unless the device is reprogrammed. The modes that can be changed by the MCU can be done so dynamically at run-time. The PLD I/O, Data Port, Address Input, Peripheral I/O and MCU RESET Modes are the only modes that must be defined before programming the device. All other modes can be changed by the MCU at run-time. See Application Note AN1171 for more detail. Table 40, page 61 summarizes which modes are available on each port. Table 41, page 61 shows how and where the different modes are configured. Each of the port operating modes are described in the following sections.
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PSD4256G6V
Figure 27. General I/O Port Architecture
DATA OUT REG. D WR ADDRESS ALE D G Q ADDRESS OUTPUT MUX PORT PIN Q
DATA OUT
MACROCELL OUTPUTS EXT CS INTERNAL DATA BUS READ MUX P D B DATA IN OUTPUT SELECT
CONTROL REG. D WR DIR REG. D WR ENABLE PRODUCT TERM (.OE) INPUT MACROCELL CPLD - INPUT
AI02885
Q
ENABLE OUT
Q
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PSD4256G6V
MCU I/O Mode In the MCU I/O mode, the MCU uses the PSD Ports to expand its own I/O ports. By setting up the CSIOP space, the ports on the PSD are mapped into the MCU address space. The addresses of the ports are listed in Table 6, page 19. A port pin can be put into MCU I/O mode by writing a 0 to the corresponding bit in the Control Register (for Ports E, F and G). The MCU I/O direction may be changed by writing to the corresponding bit in the Direction Register, or by the output enable product term. See the section entitled "Port Operating Modes", on page 58. When the pin is configured as an output, the content of the Data Out Register drives the pin. When configured as an input, the MCU can read the port input through the Data In buffer. See Figure 27, page 59. Ports A, B and C do not have Control Registers, and are in MCU I/O mode by default. They can be used for PLD I/O if they are specified in PSDsoft. PLD I/O Mode The PLD I/O Mode uses a port as an input to the CPLD's Input Macrocells (IMC), and/or as an output from the CPLD's Output Macrocells (OMC). The output can be tri-stated with a control signal. This output enable control signal can be defined Table 39. Port Operating Modes
Port Mode MCU I/O PLD I/O McellA Outputs McellB Outputs Additional Ext. CS Outputs PLD Inputs Address Out Address In Data Port Peripheral I/O JTAG ISP MCU RESET Mode2 Port A Yes Yes No No Yes No Yes No Yes No No Port B Yes Yes Yes No Yes No Yes No No No No Port C Yes No No Yes Yes No Yes No No No No Port D Yes No No No Yes No Yes No Yes No No Port E Yes No No No No Yes (A7 - 0) No No No Yes1 No Port F Yes No No Yes Yes Yes (A7 - 0) Yes Yes Yes No Yes Port G Yes No No No No Yes (A7 - 0) or (A15 - 8) No Yes No No Yes
by a product term from the PLD, or by resetting the corresponding bit in the Direction Register to 0. The corresponding bit in the Direction Register must not be set to 1 if the pin is defined for a PLD input signal in PSDsoft. The PLD I/O mode is specified in PSDsoft by declaring the port pins, and then specifying an equation in PSDsoft. Address Out Mode For MCUs with a multiplexed address/data bus, Address Out mode can be used to drive latched addresses onto the port pins. These port pins can, in turn, drive external devices. Either the output enable or the corresponding bits of both the Direction Register and Control Register must be set to a 1 for pins to use Address Out mode. This must be done by the MCU at run-time. See Table 41, page 61 for the address output pin assignments on Ports E, F and G for various MCUs. Note: Do not drive address signals with Address Out Mode to an external memory device if it is intended for the MCU to Boot from the external device. The MCU must first Boot from PSD memory so the Direction and Control register bits can be set.
Note: 1. Can be multiplexed with other I/O functions. 2. Available to Motorola 16-bit 683xx and HC16 families of MCUs.
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PSD4256G6V
Table 40. Port Operating Mode Settings
Mode Defined in PSDsoft Control Register Setting 0 (Note 4) Direction Register Setting 1 = output, 0 = input (Note 2) (Note 2) VM Register Setting JTAG Enable
MCU I/O
Declare pins only Declare pins and Logic equations Selected for MCU with non-multiplexed bus Declare pins only Declare pins or Logic equation for Input Macrocells Logic equations (PSEL0 and PSEL1) Declare pins only Specific pin logic level
N/A
N/A
PLD I/O
N/A
N/A
N/A
Data Port (Port F, G) Address Out (Port E, F, G) Address In (Port A, B, C, D, F) Peripheral I/O (Port F) JTAG ISP 3 MCU RESET Mode
N/A
N/A
N/A
N/A
1
1 (Note 2)
N/A
N/A
N/A
N/A
N/A
N/A
N/A N/A N/A
N/A N/A N/A
PIO bit = 1 N/A N/A
N/A JTAG_Enable N/A
Note: 1. N/A = Not Applicable 2. The direction of the Port A,B,C, and F pins are controlled by the Direction Register ORed with the individual output enable product term (.oe) from the CPLD AND Array. 3. Any of these three methods enables the JTAG pins on Port E. 4. Control Register setting is not applicable to Ports A, B and C.
Table 41. I/O Port Latched Address Output Assignments
MCU 80C51XA Port E (PE3-PE0) N/A(1) Port E (PE7-PE4) Address a7-a4 Address a7-a4 Port F (PF3-PF0) N/A Port F (PF7-PF4) Address a7-a4 Address a7-a4 Port G (PG3-PG0) Address a11-a8 Address a11-a8 (a3-a0 for 8bit MCU) Port G (PG7-PG4) Address a15-a12 Address a15-a12 (a7-a4 for 8bit MCU)
All Other MCUs with Multiplexed Bus
Note: 1. N/A = Not Applicable.
Address a3-a0
Address a3-a0
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PSD4256G6V
Address In Mode For MCUs that have more than 16 address signals, the higher addresses can be connected to Port A, B, C, D or F, and are routed as inputs to the PLDs. The address input can be latched in the Input Macrocell (IMC) by Address Strobe (ALE/AS, PD0). Any input that is included in the DPLD equations for the primary Flash memory, secondary Flash memory or SRAM is considered to be an address input. Data Port Mode Ports F and G can be used as a data bus port for a MCU with a non-multiplexed address/data bus. The Data Port is connected to the data bus of the MCU. The general I/O functions are disabled in Ports F and G if the ports are configured as a Data Figure 28. Peripheral I/O Mode
RD PSEL0 PSEL PSEL1 D0 - D7 DATA BUS
Port. Data Port mode is automatically configured in PSDsoft when a non-multiplexed bus MCU is selected. Peripheral I/O Mode Peripheral I/O mode can be used to interface with external 8-bit peripherals. In this mode, all of Port F serves as a tri-state, bi-directional data buffer for the MCU. Peripheral I/O mode is enabled by setting bit 7 of the VM Register to a 1. Figure 27 shows how Port A acts as a bi-directional buffer for the MCU data bus if Peripheral I/O mode is enabled. An equation for PSEL0 and/or PSEL1 must be specified in PSDsoft. The buffer is tri-stated when PSEL0 or PSEL1 is not active.
VM REGISTER BIT 7
PA0 - PA7
WR
AI02886
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PSD4256G6V
JTAG In-System Programming (ISP) Port E is JTAG compliant, and can be used for InSystem Programming (ISP). You can multiplex JTAG operations with other functions on Port E because In-System Programming (ISP) is not performed during normal system operation. For more information on the JTAG Port, see the section entitled "RESET", on page 34. MCU RESET Mode Ports F and G can be configured to operate in MCU RESET Mode. This mode is available when PSD is configured for the Motorola 16-bit 683xx and HC16 family and is active only during reset. At the rising edge of the RESET input, the MCU reads the logic level on the data bus (D15-D0) pins. The MCU then configures some of its I/O pin functions according to the logic level input on the data bus lines. Two dedicated buffers are usually enabled during RESET to drive the data bus lines to the desired logic level. The PSD can replace the two buffers by configuring Ports F and G to operate in MCU RESET Mode. In this mode, the PSD will drive the pre-defined logic level or data pattern on to the MCU data bus when RESET is active and there is no ongoing bus cycle. After RESET, Ports F and G return to the normal Data Port mode. The MCU RESET Mode is enabled and configured in PSDsoft. The user defines the logic level (data pattern) that will be drive out from Ports F and G during RESET. Port Configuration Registers (PCR) Each Port has a set of Port Configuration Registers (PCR) used for configuration. The contents of the registers can be accessed by the MCU through normal READ/WRITE bus cycles at the addresses given in Table 6, page 19. The addresses in Table 6 are the offsets in hexadecimal from the base of the CSIOP register. The pins of a port are individually configurable and each bit in the register controls its respective pin. For example, bit 0 in a register refers to bit 0 of its port. The three Port Configuration Registers (PCR), shown in Table 42, are used for setting the Port configurations. The default Power-up state for each register in Table 42 is 00h. Control Register Any bit reset to '0' in the Control Register sets the corresponding port pin to MCU I/O mode, and a 1 sets it to Address Out mode. The default mode is MCU I/O. Only Ports E, F and G have an associated Control Register. Table 42. Port Configuration Registers (PCR)
Register Name Control Direction Drive Select1 E, F, G A, B, C, D, E, F, G A, B, D, E, G Port MCU Access WRITE/READ WRITE/READ WRITE/READ
Note: 1. See Table 46, page 64 for Drive Register bit definition.
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PSD4256G6V
Direction Register The Direction Register controls the direction of data flow in the I/O Ports. Any bit set to 1 in the Direction Register causes the corresponding pin to be an output, and any bit set to 0 causes it to be an input. The default mode for all port pins is input. Figure 28, page 62 and Figure 30, page 67 show the Port Architecture diagrams for Ports A/B/C and E/F/G, respectively. The direction of data flow for Ports A, B, C and F are controlled not only by the direction register, but also by the output enable product term from the PLD AND Array. If the output enable product term is not active, the Direction Register has sole control of a given pin's direction. An example of a configuration for a Port with the three least significant bits set to output and the remainder set to input is shown in Table 45. Since Port D only contains four pins, the Direction Register for Port D has only the four least significant bits active. Drive Select Register The Drive Select Register configures the pin driver as Open Drain or CMOS. An external pull-up resistor should be used for pins configured as Open Drain. A pin can be configured as Open Drain if its corresponding bit in the Drive Select Register is set to a 1. The default pin drive is CMOS.
Table 46 shows the Drive Register for Ports A, B, D, E and G. It summarizes which pins can be configured as Open Drain outputs. Table 43. Port Pin Direction Control, Output Enable P.T. Not Defined
Direction Register Bit 0 1 Port Pin Mode Input Output
Table 44. Port Pin Direction Control, Output Enable P.T. Defined
Direction Register Bit 0 0 1 1 Output Enable P.T. 0 1 0 1 Port Pin Mode Input Output Output Output
Table 45. Port Direction Assignment Example
Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 1 Bit 1 1 Bit 0 1
Table 46. Drive Register Pin Assignment
Drive Register Port A Port B Port D Port E Port G Bit 7 Open Drain Open Drain NA(1) Open Drain Open Drain Bit 6 Open Drain Open Drain NA(1) Open Drain Open Drain Bit 5 Open Drain Open Drain NA(1) Open Drain Open Drain Bit 4 Open Drain Open Drain NA(1) Open Drain Open Drain Bit 3 Open Drain Open Drain Open Drain Open Drain Open Drain Bit 2 Open Drain Open Drain Open Drain Open Drain Open Drain Bit 1 Open Drain Open Drain Open Drain Open Drain Open Drain Bit 0 Open Drain Open Drain Open Drain Open Drain Open Drain
Note: 1. NA = Not Applicable.
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PSD4256G6V
Port Data Registers The Port Data Registers, shown in Table 47, are used by the MCU to write data to or read data from the ports. Table 47 shows the register name, the ports having each register type, and MCU access for each register type. The registers are described next. Data In Port pins are connected directly to the Data In buffer. In MCU I/O Input mode, the pin input is read through the Data In buffer. Data Out Register Stores output data written by the MCU in the MCU I/O Output mode. The contents of the Register are driven out to the pins if the Direction Register or the output enable product term is set to 1. The contents of the register can also be read back by the MCU. Output Macrocells (OMC) The CPLD Output Macrocells (OMC) occupy a location in the MCU's address space. The MCU can read the output of the Output Macrocells (OMC). If the Mask Macrocell Register bits are not set, writing to the Macrocell loads data to the Macrocell flip-flops. See the section entitled "I/O PORTS", on page 58. Mask Macrocell Register Each Mask Macrocell Register bit corresponds to an Output Macrocell (OMC) flip-flop. When the Mask Macrocell Register bit is set to a 1, loading data into the Output Macrocell (OMC) flip-flop is blocked. The default value is 0, or unblocked. Input Macrocells (IMC) The Input Macrocells (IMC) can be used to latch or store external inputs. The outputs of the Input Macrocells (IMC) are routed to the PLD input bus, and can be read by the MCU. See the section entitled "Input Macrocells (IMC)", on page 45.
Table 47. Port Data Registers
Register Name Data In Data Out Output Macrocell Mask Macrocell Input Macrocell Enable Out Port A, B, C, D, E, F, G A, B, C, D, E, F, G A, B A, B A, B, C A, B, C, F READ - input on pin WRITE/READ READ - outputs of Macrocells WRITE - loading Macrocells Flip-flop WRITE/READ - prevents loading into a given Macrocell READ - outputs of the Input Macrocells READ - the output enable control of the port driver MCU Access
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PSD4256G6V
Enable Out The Enable Out register can be read by the MCU. It contains the output enable values for a given port. A 1 indicates the driver is in output mode. A 0 indicates the driver is in tri-state and the pin is in input mode. Ports A, B and C - Functionality and Structure Ports A, B, and C have similar functionality and structure, as shown in Figure 29. The ports can be configured to perform one or more of the following functions: s MCU I/O Mode
s
CPLD Output - Macrocells McellA7-McellA0 can be connected to Port A. McellB7-McellB0 can be connected to Port B. External Chip Select (ECS7-ECS0) can be connected to Port C or Port F. CPLD Input - Via the Input Macrocells (IMC). Address In - Additional high address inputs using the Input Macrocells (IMC). Open Drain - pins PA7-PA0 can be configured to Open Drain mode.
s s
s
Figure 29. Port A, B, and C Structure
DATA OUT Register D WR PORT Pin OUTPUT MUX Q
DATA OUT
MCELLA7-MCELLA0 (Port A) MCELLB7-MCELLB0 (Port B) Ext.CS (Port C) READ MUX P D B DATA IN
INTERNAL DATA BUS
ENABLE OUT
DIR Register D WR ENABLE PRODUCT TERM (.OE) INPUT MACROCELL Q
CPLD - INPUT
AI04936B
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PSD4256G6V
Port D - Functionality and Structure Port D has four I/O pins. See Figure 30. Port D can be configured to perform one or more of the following functions: s MCU I/O mode
s
s s
Address Strobe (ALE/AS, PD0) CLKIN (PD1) as input to the Macrocells Flipflops and APD counter PSD Chip Select Input (CSI, PD2). Driving this signal High disables the Flash memory, SRAM and CSIOP. WRITE-Enable High-byte (WRH, PD3) input, or as DBE input from a MC68HC912.
CPLD Input - direct input to the CPLD, no Input Macrocells (IMC) Port D pins can be configured in PSDsoft as input pins for other dedicated functions:
s
s
Figure 30. Port D Structure
DATA OUT Register DATA OUT D WR PORT D PIN OUTPUT MUX Q
INTERNAL DATA BUS
READ MUX
P D B DATA IN
OUTPUT SELECT
DIR Register D WR Q CPLD - INPUT
AI04937
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PSD4256G6V
Port E - Functionality and Structure Port E can be configured to perform one or more of the following functions (see Figure 31, page 69): s MCU I/O Mode
s
s
CPLD Input - direct input to the CPLD, no Input Macrocells (IMC) Latched Address output - Provide latched address output as per Table 41, page 61. Data Port - connected to D7-D0 when Port F is configured as Data Port for a non-multiplexed bus Peripheral Mode MCU RESET Mode - for 16-bit Motorola 683xx and HC16 MCUs
s
In-System Programming (ISP) - JTAG port can be enabled for programming/erase of the PSD device. (See the section entitled "RESET", on page 34, for more information on JTAG programming.) Open Drain - pins can be configured in Open Drain Mode Battery Backup features - PE6 can be configured for a battery input supply, Voltage Standby (VSTBY). - PE7 can be configured as a Battery-on Indicator (VBATON), indicating when VCC is less than VBAT.
s
s s
s
s
Port G - Functionality and Structure Port G can be configured to perform one or more of the following functions: s MCU I/O Mode
s
Latched Address output - Provide latched address output as per Table 41, page 61. Open Drain - pins can be configured in Open Drain Mode Data Port - connected to D15-D8 when Port G is configured as Data Port for a non-multiplexed bus MCU RESET Mode - for 16-bit Motorola 683xx and HC16 MCUs
s
Latched Address output - Provide latched address output.
s
Port F - Functionality and Structure Port F can be configured to perform one or more of the following functions: s MCU I/O Mode
s
s
s
CPLD Output - External Chip Select (ECS7ECS0) can be connected to Port F or Port C.
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PSD4256G6V
Figure 31. Port E, F, and G Structure
DATA OUT Register D WR ADDRESS ALE D G Q ADDRESS A[ 7:0] OR A[15:8] OUTPUT MUX PORT Pin Q DATA OUT
Ext. CS (Port F) READ MUX P D B CONTROL Register D WR DIR Register D WR ENABLE PRODUCT TERM (.OE) CPLD - INPUT (Port F) Q Q ENABLE OUT DATA IN OUTPUT SELECT
INTERNAL DATA BUS
ISP or Battery Back-Up (Port E) Configuration Bit
AI04938
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
PSD4256G6V
POWER MANAGEMENT The PSD device offers configurable power saving options. These options may be used individually or in combinations, as follows: s All memory blocks in a PSD (primary Flash memory, secondary Flash memory, and SRAM) are built with power management technology. In addition to using special silicon design methodology, power management technology puts the memories into Standby Mode when address/data inputs are not changing (zero DC current). As soon as a transition occurs on an input, the affected memory "wakes up", changes and latches its outputs, then goes back to standby. The designer does not have to do anything special to achieve memory Standby Mode when no inputs are changing--it happens automatically. The PLD sections can also achieve Standby Mode when its inputs are not changing, as described for the Power Management Mode Registers (PMMR), later. s The Automatic Power Down (APD) block allows the PSD to reduce to standby current automatically. The APD Unit also blocks MCU address/data signals from reaching the memories and PLDs. This feature is available on all PSD devices. The APD Unit is described in more detail in the section entitled "Automatic Power-down (APD) Unit and Power-down Mode", on page 71. Built in logic monitors the Address Strobe of the MCU for activity. If there is no activity for a certain period (the MCU is asleep), the APD Unit initiates Power-down mode (if enabled). Once in Power-down mode, all address/data signals are blocked from reaching the PSD memories and PLDs, and the memories are deselected internally. This allows the memories and PLDs to remain in Standby Mode even if the address/data signals are changing state externally (noise, other devices on the MCU bus, etc.). Keep in
s
s
mind that any unblocked PLD input signals that are changing states keeps the PLD out of Standby Mode, but not the memories. PSD Chip Select Input (CSI, PD2) can be used to disable the internal memories, placing them in Standby Mode even if inputs are changing. This feature does not block any internal signals or disable the PLDs. This is a good alternative to using the APD Unit, especially if your MCU has a chip select output. There is a slight penalty in memory access time when PSD Chip Select Input (CSI, PD2) makes its initial transition from deselected to selected. The Power Management Mode Registers (PMMR) can be written by the MCU at run-time to manage power. All PSD devices support "blocking bits" in these registers that are set to block designated signals from reaching both PLDs. Current consumption of the PLDs is directly related to the composite frequency of the changes on their inputs (see Figure 35, page 77). Significant power savings can be achieved by blocking signals that are not used in DPLD or CPLD logic equations at run-time. PSDsoft creates a fuse map that automatically blocks the low address byte (A7-A0) or the control signals (CNTL0-CNTL2, ALE and WRITE-Enable Highbyte (WRH/DBE, PD3)) if none of these signals are used in PLD logic equations. PSD devices have a Turbo bit in PMMR0. This bit can be set to turn the Turbo mode off (the default is with Turbo mode turned on). While Turbo mode is off, the PLDs can achieve standby current when no PLD inputs are changing (zero DC current). Even when inputs do change, significant power can be saved at lower frequencies (AC current), compared to when Turbo mode is on. When the Turbo mode is on, there is a significant DC current component, and the AC component is higher.
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PSD4256G6V
Automatic Power-down (APD) Unit and Power-down Mode The APD Unit, shown in Figure 32, puts the PSD the appropriate bits in the Power Management into Power-down mode by monitoring the activity Mode Registers (PMMR). The blocked signals of Address Strobe (ALE/AS, PD0). If the APD Unit include MCU control signals and the common is enabled, as soon as activity on Address Strobe CLKIN (PD1). Note that blocking CLKIN (PD1) (ALE/AS, PD0) stops, a four bit counter starts from the PLDs does not block CLKIN (PD1) counting. If Address Strobe (ALE/AS, PD0) refrom the APD Unit. mains inactive for fifteen clock periods of CLKIN s All PSD memories enter Standby Mode and are (PD1), Power-down (PDN) goes High, and the drawing standby current. However, the PLDs PSD enters Power-down mode, as discussed and I/O ports blocks do not go into Standby next. Mode because you do not want to have to wait for the logic and I/O to "wake-up" before their Power-down Mode outputs can change. See Table 49, page 71 for By default, if you enable the APD Unit, PowerPower-down mode effects on PSD ports. down mode is automatically enabled. The device s Typical Standby current is or the order of A. enters Power-down mode if Address Strobe (ALE/ This standby current value assumes that there AS, PD0) remains inactive for fifteen periods of are no transitions on any PLD input. CLKIN (PD1). The following should be kept in mind when the PSD is in Power-down mode: Table 48. Effect of Power-down Mode on Ports s If Address Strobe (ALE/AS, PD0) starts pulsing Port Function Pin Level again, the PSD returns to normal operation. The MCU I/O No Change PSD also returns to normal operation if either PSD Chip Select Input (CSI, PD2) is Low or the PLD Out No Change Reset (RESET) input is High. Address Out Undefined s The MCU address/data bus is blocked from all memory and PLDs. Data Port Tri-State s Various signals can be blocked (prior to PowerPeripheral I/O Tri-State down mode) from entering the PLDs by setting Figure 32. APD Unit
APD EN PMMR0 BIT 1=1 TRANSITION DETECTION ALE CLR PD Secondary Flash Memory Select Primary Flash Memory Select PLD SRAM Select POWER DOWN (PDN) Select DISABLE BUS INTERFACE
RESET CSI CLKIN EDGE DETECT
APD COUNTER PD
DISABLE Primary and Secondary FLASH Memory and SRAM
AI04939
Table 49. PSD Timing and Standby Current During Power-down Mode
Mode Power-down PLD Propagation Delay Normal tPD (Note 1) Memory Access Time No Access Access Recovery Time to Normal Access tLVDV Typical Standby Current 50 A (Note 2)
Note: 1. Power-down does not affect the operation of the PLD. The PLD operation in this mode is based only on the Turbo bit. 2. Typical current consumption assuming no PLD inputs are changing state and the PLD Turbo bit is 0.
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PSD4256G6V
Other Power Saving Options The PSD offers other reduced power saving options that are independent of the Power-down mode. Except for the SRAM Standby and PSD Chip Select Input (CSI, PD2) features, they are enabled by setting bits in PMMR0 and PMMR2 (as summarized in Table 23 and Table 24, page 23). PLD Power Management The power and speed of the PLDs are controlled by the Turbo bit (bit 3) in PMMR0. By setting the bit to 1, the Turbo mode is off and the PLDs consume the specified standby current when the inputs are not switching for an extended time of 70 ns. The propagation delay time is increased after the Turbo bit is set to 1 (turned off) when the inputs change at a composite frequency of less than 15 MHz. When the Turbo bit is reset to '0' (turned on), the PLDs run at full power and speed. The Turbo bit affects the PLD's DC power, AC power, and propagation delay. See the AC and DC characteristics tables for PLD timing values (Table 68). Blocking MCU control signals with the PMMR2 bits can further reduce PLD AC power consumption. SRAM Standby Mode (Battery Backup) The PSD supports a battery backup mode in which the contents of the SRAM are retained in the event of a power loss. The SRAM has Voltage Standby (VSTBY, PE6) that can be connected to an external battery. When VCC becomes lower than V STBY then the PSD automatically connects to Voltage Standby (VSTBY, PE6) as a power source to the SRAM. The SRAM standby current (ISTBY) is typically 0.5 A. The SRAM data retention voltage is 2V minimum. The Battery-on Indicator (VBATON) can be routed to PE7. This signal indicates when the VCC has dropped below V STBY, and that the SRAM is running on battery power. PSD Chip Select Input (CSI, PD2) PD2 of Port D can be configured in PSDsoft as PSD Chip Select Input (CSI). When Low, the signal selects and enables the internal primary Flash memory, secondary Flash memory, SRAM, and I/ O blocks for READ or WRITE operations involving the PSD. A High on PSD Chip Select Input (CSI, PD2) disables the primary Flash memory, secondary Flash memory, and SRAM, and reduces the PSD power consumption. However, the PLD and
I/O signals remain operational when PSD Chip Select Input (CSI, PD2) is High. There may be a timing penalty when using PSD Chip Select Input (CSI, PD2) depending on the speed grade of the PSD that you are using. See the timing parameter tSLQV in Table 68. Input Clock The PSD provides the option to turn off CLKIN (PD1) to the PLD to save AC power consumption. CLKIN (PD1) is an input to the PLD AND Array and the Output Macrocells (OMC). During Power-down mode, or, if CLKIN (PD1) is not being used as part of the PLD logic equation, the clock should be disabled to save AC power. CLKIN (PD1) is disconnected from the PLD AND Array or the Macrocells block by setting bits 4 or 5 to a 1 in PMMR0. Figure 33. Enable Power-down Flow Chart
RESET
Enable APD Set PMMR0 Bit 1 = 1
OPTIONAL
Disable desired inputs to PLD by setting PMMR0 bits 4 and 5 and PMMR2 bits 0 to 6.
No
ALE/AS idle for 15 CLKIN clocks? Yes PSD in Power Down Mode
AI04940
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PSD4256G6V
Input Control Signals The PSD provides the option to turn off the address input (A7-A0) and input control signals (CNTL0, CNTL1, CNTL2, Address Strobe (ALE/ AS, PD0) and WRITE-Enable High-byte (WRH/ DBE, PD3)) to the PLD to save AC power consumption. These signals are inputs to the PLD Table 50. ADP Counter Operation
APD Enable Bit 0 1 1 1 ALE PD Polarity X X 1 0 ALE Level X Pulsing 1 0 APD Counter Not Counting Not Counting Counting (Generates PDN after 15 Clocks) Counting (Generates PDN after 15 Clocks)
AND Array. During Power-down mode, or, if any of them are not being used as part of the PLD logic equation, these control signals should be disabled to save AC power. They are disconnected from the PLD AND Array by setting bits 0, 2, 3, 4, 5 and 6 to a 1 in PMMR2.
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PSD4256G6V
RESET TIMING AND DEVICE STATUS AT RESET Power-on RESET Upon Power-up, the PSD requires a Reset (RESET) pulse of duration t NLNH-PO (minimum 1ms) after V CC is steady. During this period, the device loads internal configurations, clears some of the registers and sets the Flash memory into Operating mode. After the rising edge of Reset (RESET), the PSD remains in the RESET Mode for an additional period, tOPR (maximum 120 ns), before the first memory access is allowed. The PSD Flash memory is reset to the READ Mode upon Power-up. Sector Select (FS0-FS15 and CSBOOT0-CSBOOT3) must all be Low, WRITE Strobe (WR/WRL, CNTL0) High, during Power-on RESET for maximum security of the data contents and to remove the possibility of data being written on the first edge of WRITE Strobe (WR/WRL, CNTL0). Any Flash memory WRITE cycle initiation is prevented automatically when VCC is below VLKO. Warm RESET Once the device is up and running, the device can be reset with a pulse of a much shorter duration, tNLNH (minimum 150ns). The same tOPR period is
needed before the device is operational after Warm RESET. Figure 34, page 75 shows the timing of the Power-up and Warm RESET. I/O Pin, Register and PLD Status at RESET Table 51 shows the I/O pin, register and PLD status during Power-on RESET, Warm RESET and Power-down mode. PLD outputs are always valid during Warm RESET, and they are valid in Poweron RESET once the internal PSD Configuration bits are loaded. This loading of PSD is completed typically long before the V CC ramps up to operating level. Once the PLD is active, the state of the outputs are determined by equations specified in PSDsoft. RESET of Flash Memory Erase and Program Cycles An external Reset (RESET) also resets the internal Flash memory state machine. During a Flash memory Program or Erase cycle, Reset (RESET) terminates the cycle and returns the Flash memory to the READ Mode within a period of tNLNH-A (minimum 25s).
Table 51. Status During Power-on RESET, Warm RESET, and Power-down Mode
Port Configuration MCU I/O PLD Output Address Out Data Port Peripheral I/O Power-on RESET Input mode Valid after internal PSD configuration bits are loaded Tri-stated Tri-stated Tri-stated Warm Reset Input mode Valid Tri-stated Tri-stated Tri-stated Power-down Mode Unchanged Depends on inputs to PLD (addresses are blocked in PD mode) Not defined Tri-stated Tri-stated
Register PMMR0 and PMMR2 Macrocells Flip-flop status
Power-On Reset Cleared to 0 Cleared to 0 by internal Power-On Reset Initialized, based on the selection in PSDsoft Configuration menu Cleared to 0
Warm Reset Unchanged Depends on .re and .pr equations Initialized, based on the selection in PSDsoft Configuration menu Cleared to 0
Power-down Mode Unchanged Depends on .re and .pr equations Unchanged Unchanged
VM Register(1) All other registers
Note: 1. The SR_code and Peripheral Mode bits in the VM Register are always cleared to '0' on Power-on RESET or Warm RESET.
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PSD4256G6V
Figure 34. Reset (RESET) Timing
VCC
VCC(min) tNLNH tNLNH-A Warm Reset
tNLNH-PO Power-On Reset
tOPR
tOPR
RESET
AI02866b
PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE JTAG_ON = PSDsoft_enabled + The JTAG Serial Interface on the PSD can be enabled on Port E (see Table 52). All memory blocks /* An NVM configuration bit inside (primary Flash memory and secondary Flash the PSD is set by the designer in memory), PLD logic, and PSD Configuration bits the PSDsoft Configuration utilimay be programmed through the JTAG-ISC Serial ty. This dedicates the pins for Interface. A blank device can be mounted on a JTAG at all times (compliant with printed circuit board and programmed using JTAG In-System Programming (ISP). IEEE 1149.1 */ The standard JTAG signals (IEEE 1149.1) are Microcontroller_enabled + TMS, TCK, TDI, and TDO. Two additional signals, /* The microcontroller can set a TSTAT and TERR, are optional JTAG extensions bit at run-time by writing to the used to speed up Program and Erase cycles. PSD register, JTAG Enable. This By default, on a blank PSD (as shipped from the register is located at address factory, or after erasure), four pins on Port E are enabled for the basic JTAG signals TMS, TCK, CSIOP + offset C7h. Setting the TDI, and TDO. JTAG_ENABLE bit in this register See Application Note AN1153 for more details on will enable the pins for JTAG use. JTAG In-System Programming (ISP). This bit is cleared by a PSD reset Standard JTAG Signals or the microcontroller. See Table The standard JTAG signals (TMS, TCK, TDI, and 21 for bit definition. */ TDO) can be enabled by any of three different conPSD_product_term_enabled; ditions that are logically ORed. When enabled, /* A dedicated product term (PT) TDI, TDO, TCK, and TMS are inputs, waiting for a inside the PSD can be used to enserial command from an external JTAG controller device (such as FlashLINK or Automated Test able the JTAG pins. This PT has Equipment). When the enabling command is rethe reserved name JTAGSEL. Once ceived from the external JTAG controller device, defined as a node in PSDabel, the TDO becomes an output and the JTAG channel is designer can write an equation for fully functional inside the PSD. The same comJTAGSEL. This method is used when mand that enables the JTAG channel may optionally enable the two additional JTAG pins, TSTAT the Port E JTAG pins are multiand TERR. plexed with other I/O signals. It The following symbolic logic equation specifies the is recommended to tie logically conditions enabling the four basic JTAG pins the node JTAGSEL to the JEN\ sig(TMS, TCK, TDI, and TDO) on their respective nal on the Flashlink cable when Port E pins. For purposes of discussion, the logic multiplexing JTAG signals. See Aplabel JTAG_ON is used. When JTAG_ON is true, plication Note 1153 for details. the four pins are enabled for JTAG. When JTAG_ON is false, the four pins can be used for */ general PSD I/O.
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PSD4256G6V
The state of the PSD Reset (RESET) signal does not interrupt (or prevent) JTAG operations if the JTAG pins are dedicated by an NVM configuration bit (via PSDsoft). However, Reset (RESET) will prevent or interrupt JTAG operations if the JTAG Enable Register (as shown in Table 21, page 22) is used to enable the JTAG pins. The PSD supports JTAG In-System-Programmability (ISP) commands, but not Boundary Scan. ST's PSDsoft software tool and FlashLINK JTAG programming cable implement the JTAG In-System-Programmability (ISP) commands. JTAG Extensions TSTAT and TERR are two JTAG extension signals enabled by a JTAG command received over the four standard JTAG pins (TMS, TCK, TDI, and TDO). They are used to speed Program and Erase cycles by indicating status on PSD pins instead of having to scan the status out serially using the standard JTAG channel. See Application Note AN1153. TERR indicates if an error has occurred when erasing a sector or programming in Flash memory. This signal goes Low (active) when an Error condition occurs, and stays Low until a specific JTAG command is executed or a Reset (RESET) pulse is received after an "ISC_DISABLE" command. TSTAT behaves the same as Ready/Busy (PE4) described in the section entitled "Ready/Busy (PE4)", on page 26. TSTAT is High when the PSD4256G6V device is in READ Mode (primary Flash memory and secondary Flash memory contents can be read). TSTAT is Low when Flash memory Program or Erase cycles are in progress, and also when data is being written to the secondary Flash memory. TSTAT and TERR can be configured as opendrain type signals with a JTAG command. Note: The state of Reset (Reset) does not interrupt (or prevent) JTAG operations if the JTAG signals are dedicated by an NVM Configuration bit (via PSDsoft). However, Reset (Reset) prevents or interrupts JTAG operations if the JTAG Enable Register (as shown in Table 21, page 22) is used to enable the JTAG signals. Security and Flash memory Protection When the security bit is set, the device cannot be read on a Device Programmer or through the JTAG Port. When using the JTAG Port, only a Full Chip Erase command is allowed. All other Program, Erase and Verify commands are blocked. Full Chip Erase returns the device to a non-secured blank state. The Security Bit can be set in PSDsoft. All primary Flash memory and secondary Flash memory sectors can individually be sector protected against erasure. The sector protect bits can be set in PSDsoft. Table 52. JTAG Port Signals
Port E Pin PE0 PE1 PE2 PE3 PE4 PE5 JTAG Signals TMS TCK TDI TDO TSTAT TERR Description Mode Select Clock Serial Data In Serial Data Out Status Error Flag
INITIAL DELIVERY STATE When delivered from ST, the PSD device has all bits in the memory and PLDs set to 1. The PSD Configuration Register bits are set to 0. The code, configuration, and PLD logic are loaded using the
programming procedure. Information for programming the device is available directly from ST. Please contact your local sales representative.
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PSD4256G6V
AC/DC PARAMETERS These tables describe the AD and DC parameters of the PSD4256G6V: s DC Electrical Specification
s
- Power-down and RESET Timing The following are issues concerning the parameters presented: s In the DC specification the supply current is given for different modes of operation. Before calculating the total power consumption, determine the percentage of time that the PSD is in each mode. Also, the supply power is considerably different if the Turbo bit is 0. s The AC power component gives the PLD, Flash memory, and SRAM mA/MHz specification. Figure 35 shows the PLD mA/MHz as a function of the number of Product Terms (PT) used. s In the PLD timing parameters, add the required delay when Turbo bit is 0.
AC Timing Specification PLD Timing - Combinatorial Timing - Synchronous Clock Mode - Asynchronous Clock Mode - Input Macrocell Timing MCU Timing - READ Timing - WRITE Timing - Peripheral Mode Timing
Figure 35. PLD ICC / Frequency Consumption
60 VCC = 3V 50 ICC - (mA) 40
RB O
T
O URB
ON (
100%
)
O
FF
TU
30 20 10
TURB
(2 O ON
5%)
TU
0 0
RB
5
O
OF
F
PT 100% PT 25%
10
15
20
25
AI04942
HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)
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PSD4256G6V
Table 53. Example of PSD Typical Power Calculation at VCC = 3.0V (with Turbo Mode On)
Conditions Highest Composite PLD input frequency (Freq PLD) MCU ALE frequency (Freq ALE) % Flash memory Access % SRAM access % I/O access Operational Modes % Normal % Power-down Mode Number of product terms used (from fitter report) % of total product terms Turbo Mode = 54 PT = 54/217 = 25% = ON Calculation (using typical values) ICC total = Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc)) = Ipwrdown x %pwrdown + % normal x (%flash x 1.2 mA/MHz x Freq ALE + %SRAM x 0.8 mA/MHz x Freq ALE + % PLD x 1.1 mA/MHz x Freq PLD + #PT x 200 A/PT) = 50 A x 0.90 + 0.1 x (0.8 x 1.2 mA/MHz x 4 MHz + 0.15 x 0.8 mA/MHz x 4 MHz + 1.1 mA/MHz x 8 MHz + 54 x 0.2 mA/PT) = 45 A + 0.1 x (3.84 + 0.48 + 8.8 + 10.8 mA) = 45 A + 0.1 x 23.92 = 45 A + 2.39 mA = 2.43 mA This is the operating power with no Flash memory Program or Erase cycles in progress. Calculation is based on IOUT = 0 mA. = 10% = 90% = 8 MHz = 4 MHz = 80% = 15% = 5% (no additional power above base)
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PSD4256G6V
Table 54. Example of PSD Typical Power Calculation at VCC = 3.0V (with Turbo Mode Off)
Conditions Highest Composite PLD input frequency (Freq PLD) MCU ALE frequency (Freq ALE) % Flash memory Access % SRAM access % I/O access Operational Modes % Normal % Power-down Mode Number of product terms used (from fitter report) % of total product terms Turbo Mode = 54 PT = 54/217 = 25% = Off Calculation (using typical values) ICC total = Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc)) = Ipwrdown x %pwrdown + % normal x (%flash x 1.2 mA/MHz x Freq ALE + %SRAM x 0.8 mA/MHz x Freq ALE + % PLD x (from graph using Freq PLD)) = 50 A x 0.90 + 0.1 x (0.8 x 1.2 mA/MHz x 4 MHz + 0.15 x 0.8 mA/MHz x 4 MHz + 15 mA) = 45 A + 0.1 x (3.84 + 0.48 + 15) = 45 A + 0.1 x 18.84 = 45 A + 1.94 mA = 1.98 mA This is the operating power with no Flash memory Program or Erase cycles in progress. Calculation is based on IOUT = 0 mA. = 10% = 90% = 8 MHz = 4 MHz = 80% = 15% = 5% (no additional power above base)
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PSD4256G6V
MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not imTable 55. Absolute Maximum Ratings
Symbol TSTG TLEAD VIO VCC VPP VESD Storage Temperature Lead Temperature during Soldering (20 seconds max.)1 Input and Output Voltage (Q = VOH or Hi-Z) Supply Voltage Device Programmer Supply Voltage Electrostatic Discharge Voltage (Human Body model) 2 -0.6 -0.6 -0.6 -2000 Parameter Min. -65 Max. 150 235 4.0 4.0 13.5 2000 Unit C C V V V V
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Note: 1. IPC/JEDEC J-STD-020A 2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 , R2=500 )
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PSD4256G6V
DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the MeasureTable 56. Operating Conditions
Symbol VCC TA Ambient Operating Temperature (commercial) 0 70 C Supply Voltage Ambient Operating Temperature (industrial) Parameter Min. 2.7 -40 Max. 3.6 85 Unit V C
ment Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters.
Table 57. AC Symbols for PLD Timing
Signal Letters A C D E I L N P R S T W B M Address Input CEout Output Input Data E Input Interrupt Input ALE Input RESET Input or Output Port Signal Output UDS, LDS, DS, RD, PSEN Inputs Chip Select Input R/W Input WR Input VSTBY Output Output Macrocell t L H V X Z PW Time Logic Level Low or ALE Logic Level High Valid No Longer a Valid Logic Level Float Pulse Width Signal Behavior
Example: tAVLX - Time from Address Valid to ALE Invalid. Table 58. AC Measurement Conditions
Symbol CL Load Capacitance Parameter Min. 30 Max. Unit pF
Note: 1. Output Hi-Z is defined as the point where data out is no longer driven.
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PSD4256G6V
Table 59. Capacitance
Symbol CIN COUT CVPP Parameter Input Capacitance (for input pins) Output Capacitance (for input/ output pins) Capacitance (for CNTL2/VPP) Test Condition VIN = 0V VOUT = 0V VPP = 0V Typ.2 4 8 18 Max. 6 12 25 Unit pF pF pF
Note: 1. Sampled only, not 100% tested. 2. Typical values are for T A = 25C and nominal supply voltages.
Figure 36. AC Measurement I/O Waveform
Figure 37. AC Measurement Load Circuit
2.0 V
0.9VCC Test Point 0V
AI04947
400 1.5V Device Under Test
CL = 30 pF (Including Scope and Jig Capacitance)
AI04948
Figure 38. Switching Waveforms - Key
WAVEFORMS INPUTS OUTPUTS
STEADY INPUT
STEADY OUTPUT
MAY CHANGE FROM HI TO LO MAY CHANGE FROM LO TO HI
WILL BE CHANGING FROM HI TO LO WILL BE CHANGING LO TO HI
DON'T CARE
CHANGING, STATE UNKNOWN
OUTPUTS ONLY
CENTER LINE IS TRI-STATE
AI03102
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PSD4256G6V
Table 60. DC Characteristics
Symbol VIH VIL VIH1 VIL1 VHYS VLKO Parameter High Level Input Voltage Low Level Input Voltage Conditions 2.7V < VCC < 3.6V 2.7V < VCC < 3.6V Min. 0.7VCC -0.5 0.8VCC -0.5 0.3 1.5 IOL = 20 A, VCC = 2.7V Output Low Voltage IOL = 4 mA, VCC = 2.7V Output High Voltage Except VSTBY On Output High Voltage VSTBY On SRAM Standby Voltage SRAM Standby Current Idle Current (VSTBY input) SRAM Data Retention Voltage Standby Supply Current for Power-down Mode Input Leakage Current Output Leakage Current VCC = 0V VCC > VSTBY Only on VSTBY CSI >VCC -0.3V (Notes 2,3) VSS < VIN < VCC 0.45 < VIN < VCC PLD_TURBO = Off, f = 0 MHz (Note 3) PLD_TURBO = On, f = 0 MHz During Flash memory WRITE/Erase Only Read only, f = 0 MHz SRAM PLD AC Adder ICC (AC) (Note 5) SRAM AC Adder
Note: 1. 2. 3. 4. 5.
Typ.
Max. VCC +0.5 0.8 VCC +0.5 0.2VCC -0.1
Unit V V V V V
RESET High Level Input Voltage (Note 1) RESET Low Level Input Voltage RESET Pin Hysteresis VCC (min) for Flash Erase and Program (Note 1)
2.3 0.01 0.15 0.1 0.45
V V V V V V
VOL
VOH VOH1 VSTBY ISTBY IIDLE VDF ISB ILI ILO
IOH = -20 A, VCC = 2.7V IOH = -1 mA, VCC = 2.7V IOH1 = -1 A
2.6 2.3 VSTBY - 0.8 2.0
2.69 2.4
VCC 0.5 1 0.1
V A A V
-0.1 2 50 -1 -10 0.1 5 0 200 10 0 0 note 1.2 0.8
4
100 1 10
A A A A/ PT
PLD Only ICC (DC) Operating (Note 5) Supply Current Flash memory
400 25 0 0
A/ PT mA mA mA
f = 0 MHz
Flash memory AC Adder
1.8 1.5
mA/ MHz mA/ MHz
Reset (RESET) has hysteresis. VIL1 is valid at or below 0.2VCC -0.1. VIH1 is valid at or above 0.8VCC. CSI deselected or internal PD is active. PLD is in non-Turbo mode, and none of the inputs are switching. Please see Figure 35, page 77 for the PLD current calculation. IOUT = 0 mA
Note: 1. Conditions (in addition to those in Table 56, VCC = 4.5 to 5.5V): V SS = 0V; CL for Port 0, ALE and PSEN output is 100pF; CL for other outputs is 80pF
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PSD4256G6V
Figure 39. Input to Output Disable / Enable
INPUT
tER INPUT TO OUTPUT ENABLE/DISABLE
tEA
AI02863
Table 61. CPLD Combinatorial Timing
-10 Symbol Parameter CPLD Input Pin/Feedback to CPLD Combinatorial Output CPLD Input to CPLD Output Enable CPLD Input to CPLD Output Disable CPLD Register Clear or Preset Delay CPLD Register Clear or Preset Pulse Width CPLD Array Delay Any Macrocell 28 23 +4 Conditions Min tPD tEA tER tARP tARPW tARD Max 38 43 43 38 PT Aloc +4 Turbo Off + 20 + 20 + 20 + 20 + 20 Unit
ns ns ns ns ns ns
Table 62. CPLD Macrocell Synchronous Clock Mode Timing
-10 Symbol Parameter Maximum Frequency External Feedback fMAX Maximum Frequency Internal Feedback (fCNT) Maximum Frequency Pipelined Data tS tH tCH tCL tCO tARD tMIN Input Setup Time Input Hold Time Clock High Time Clock Low Time Clock to Output Delay CPLD Array Delay Minimum Clock Period 1 Clock Input Clock Input Clock Input Any Macrocell tCH+tCL 22 Conditions Min 1/(tS+tCO) 1/(tS+tCO-10) 1/(tCH+tCL) 18 0 11 11 26 23 +4 Max 22.7 29.4 45.0 +4 + 20 PT Aloc Turbo Off Unit
MHz MHz MHz ns ns ns ns ns ns ns
Note: 1. CLKIN (PD1) t CLCL = tCH + tCL.
84/100
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
PSD4256G6V
Table 63. CPLD Macrocell Asynchronous Clock Mode Timing
-10 Symbol Parameter Maximum Frequency External Feedback fMAXA Maximum Frequency Internal Feedback (fCNTA) Maximum Frequency Pipelined Data tSA tHA tCHA tCLA tCOA tARD tMINA Input Setup Time Input Hold Time Clock High Time Clock Low Time Clock to Output Delay CPLD Array Delay Minimum Clock Period Any Macrocell 1/fCNTA 32 Conditions Min 1/(tSA+tCOA) 1/(tSA+tCOA-10) 1/(tCHA+tCLA) 8 10 15 12 34 23 +4 + 20 + 20 + 20 Max 23.8 31.25 38.4 +4 + 20 PT Aloc Turbo Off Unit
MHz MHz MHz ns ns ns ns ns ns ns
Figure 40. Synchronous Clock Mode Timing - PLD
tCH tCL
CLKIN
tS INPUT
tH
tCO REGISTERED OUTPUT
AI02860
Figure 41. Asynchronous RESET / Preset
tARPW
RESET/PRESET INPUT tARP REGISTER OUTPUT
AI02864
85/100
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PSD4256G6V
Figure 42. Asynchronous Clock Mode Timing (product term clock)
tCHA tCLA
CLOCK
tSA
tHA
INPUT tCOA REGISTERED OUTPUT
AI02859
Figure 43. Input Macrocell Timing (Product Term Clock)
t INH
PT CLOCK
t INL
t IS
INPUT
t IH
OUTPUT
t INO
AI03101
Table 64. Input Macrocell Timing
-10 Symbol tIS tIH tINH tINL tINO Parameter Input Setup Time Input Hold Time NIB Input High Time NIB Input Low Time NIB Input to Combinatorial Delay Conditions Min (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) 0 25 13 12 55 +4 + 20 + 20 Max PT Aloc Turbo Off Unit ns ns ns ns ns
Note: 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to t AVLX and tLXAX.
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PSD4256G6V
Table 65. Program, WRITE and Erase Times
Symbol Flash Program Flash Bulk Erase1 (pre-programmed) Flash Bulk Erase (not pre-programmed) tWHQV3 tWHQV2 tWHQV1 Sector Erase (pre-programmed) Sector Erase (not pre-programmed) Byte Program Program / Erase Cycles (per Sector) tWHWLO tQ7VQV Sector Erase Time-Out DQ7 Valid to Output (DQ7-DQ0) Valid (Data Polling)2,3 100,000 100 30 Parameter Min. Typ. 8.5 3 10 1 2.2 14 1200 30 30 Max. Unit s s s s s s cycles s ns
Note: 1. Programmed to all zero before erase. 2. The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading. 3. DQ7 is DQ15 for Motorola MCU with 16-bit data bus.
Figure 44. Peripheral I/O WRITE Timing Diagram
ALE /AS
A / D BUS
ADDRESS
DATA OUT
tWLQV WR
(PF)
tWHQZ (PF)
tDVQV (PF) PORT F DATA OUT
AI05741
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PSD4256G6V
Figure 45. READ Timing Diagram
tAVLX ALE /AS tLVLX A/D MULTIPLEXED BUS ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS tSLQV CSI tRLQV tRLRH RD (PSEN, DS) tRHQZ tRHQX ADDRESS VALID tAVQV ADDRESS VALID DATA VALID tLXAX
1
DATA VALID
tEHEL E tTHEH tELTL
R/ W
tAVPV ADDRESS OUT
AI02895
Note: 1. tAVLX and tLXAX are not required for 80C251 in Page Mode or 80C51XA in Burst Mode.
88/100
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PSD4256G6V
Table 66. READ Timing
-10 Symbol tLVLX tAVLX tLXAX Parameter ALE or AS Pulse Width Address Setup Time Address Hold Time (Note 2) (Note 2) 2.7 < VCC < 3.6V (Note 2) tAVQV Address Valid to Data Valid 3.0 < VCC < 3.6V (Note 2) CS Valid to Data Valid RD to Data Valid tRLQV RD or PSEN to Data Valid on 80C51XA RD Data Hold Time RD Pulse Width RD to Data High-Z E Pulse Width R/W Setup Time to Enable R/W Hold Time After Enable Address Input Valid to Address Output Delay (Note 3) (Note 1) 38 10 0 35 (Note 1) 0 36 38 (Note 3) 90 100 35 45 + 20 ns ns ns ns ns ns ns ns ns ns ns Conditions Min 22 7 8 100 + 20 Max Turbo Off Unit ns ns ns ns
tSLQV
tRHQX tRLRH tRHQZ tEHEL tTHEH tELTL tAVPV
Note: 1. 2. 3. 4.
RD timing has the same timing as DS, LDS, UDS, and PSEN signals. Any input used to select an internal PSD function. In multiplexed mode latched address generated from ADIO delay to address output on any Port. RD timing has the same timing as DS, LDS, and UDS signals.
89/100
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PSD4256G6V
Figure 46. WRITE Timing Diagram
tAVLX ALE / AS t LVLX A/D MULTIPLEXED BUS ADDRESS VALID tAVWL ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS tSLWL CSI tDVWH WR (DS) t WLWH t WHDX t WHAX ADDRESS VALID DATA VALID DATA VALID t LXAX
t EHEL E t THEH R/ W t WLMV tAVPV ADDRESS OUT t WHPV STANDARD MCU I/O OUT t ELTL
AI02896
90/100
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PSD4256G6V
Table 67. WRITE Timing
-10 Symbol tLVLX tAVLX tLXAX tAVWL tSLWL tDVWH tWHDX tWLWH tWHAX1 tWHAX2 tWHPV tDVMV tAVPV tWLMV
Note: 1. 2. 3. 4. 5. 6. 7.
Parameter ALE or AS Pulse Width Address Setup Time Address Hold Time Address Valid to Leading Edge of WR CS Valid to Leading Edge of WR WR Data Setup Time WR Data Hold Time WR Pulse Width Trailing Edge of WR to Address Invalid Trailing Edge of WR to DPLD Address Invalid Trailing Edge of WR to Port Output Valid Using I/O Port Data Register Data Valid to Port Output Valid Using Macrocell Register Preset/Clear Address Input Valid to Address Output Delay WR Valid to Port Output Valid Using Macrocell Register Preset/Clear
Conditions Min 22 (Note 1) (Note 1) (Notes 1,3) (Note 3) (Note 3) (Note 3,7) (Note 3) (Note 3) (Note 3,6) (Note 3) (Notes 3,5) (Note 2) (Notes 3,4) 7 8 15 15 40 5 40 8 0 45 65 35 65 Max
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns
Any input used to select an internal PSD function. In multiplexed mode, latched address generated from ADIO delay to address output on any port. WR has the same timing as E, LDS, UDS, WRL, and WRH signals. Assuming data is stable before active WRITE signal. Assuming WRITE is active before data becomes valid. tWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory. tWHAX is 11 ns when writing to the Output Macrocell Registers.
91/100
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PSD4256G6V
Figure 47. Peripheral I/O READ Timing Diagram
ALE /AS
A/D BUS
ADDRESS
DATA VALID
tAVQV (PF) tSLQV (PF) CSI tRLQV (PF) RD tRLRH (PF) tQXRH (PF) tRHQZ (PF)
tDVQV (PF) DATA ON PORT F
AI05740
Table 68. Port F Peripheral Data Mode READ Timing
-10 Symbol tAVQV-PF tSLQV-PF tRLQV-PF tDVQV-PF tQXRH-PF tRLRH-PF tRHQZ-PF Parameter Address Valid to Data Valid CSI Valid to Data Valid RD to Data Valid RD to Data Valid 8031 Mode Data In to Data Out Valid RD Data Hold Time RD Pulse Width RD to Data High-Z (Note 1) (Note 1) 0 35 38 (Notes 1,4) Conditions Min (Note 3) Max 50 50 35 45 34 Turbo Off + 20 + 20 Unit ns ns ns ns ns ns ns ns
92/100
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PSD4256G6V
Table 69. Port F Peripheral Data Mode WRITE Timing
-10 Symbol tWLQV-PF tDVQV-PF tWHQZ-PF
Note: 1. 2. 3. 4. 5.
Parameter WR to Data Propagation Delay Data to Port A Data Propagation Delay WR Invalid to Port A Tri-state
Conditions Min (Note 2) (Note 5) (Note 2) Max 40 35 33
Unit ns ns ns
RD has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode). WR has the same timing as the E, LDS, UDS, WRL, and WRH signals. Any input used to select Port F Data Peripheral mode. Data is already stable on Port F. Data stable on ADIO pins to data on Port F.
Table 70. Power-down Timing
-10 Symbol tLVDV tCLWH Parameter ALE Access Time from Power-down Maximum Delay from APD Enable to Internal PDN Valid Signal Using CLKIN (PD1) 15 * tCLCL1 Conditions Min Max 128 ns s Unit
Table 71. Reset (RESET) Timing
Symbol tNLNH tNLNH-PO tNLNH-A tOPR Parameter RESET Active Low Time 1 Power-on RESET Active Low Time Warm RESET Active Low Time 2 RESET High to Operational Device Conditions Min 300 1 25 300 Max Unit ns ms s ns
Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles. 2. Warm RESET aborts Flash memory Program or Erase cycles, and puts the device in READ Mode.
Figure 48. Reset (RESET) Timing Diagram
VCC
VCC(min) tNLNH tNLNH-A Warm Reset
tNLNH-PO Power-On Reset
tOPR
tOPR
RESET
AI02866b
Table 72. V STBYON Timing
Symbol tBVBH tBXBL Parameter VSTBY Detection to VSTBYON Output High VSTBY Off Detection to VSTBYON Output Low Conditions (Note 1) (Note 1) Min Typ 20 20 Max Unit s s
Note: 1. VSTBYON timing is measured at VCC ramp rate of 2ms.
93/100
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PSD4256G6V
Figure 49. ISC Timing Diagram
t ISCCH
TCK
t ISCCL t ISCPSU t ISCPH
TDI/TMS
t ISCPZV t ISCPCO
ISC OUTPUTS/TDO
t ISCPVZ
ISC OUTPUTS/TDO
AI02865
Table 73. ISC Timing
-10 Symbol Parameter Clock (TCK, PC1) Frequency (except for PLD) Clock (TCK, PC1) High Time (except for PLD) Clock (TCK, PC1) Low Time (except for PLD) Clock (TCK, PC1) Frequency (PLD only) Clock (TCK, PC1) High Time (PLD only) Clock (TCK, PC1) Low Time (PLD only) ISC Port Set Up Time ISC Port Hold Up Time ISC Port Clock to Output ISC Port High-Impedance to Valid Output ISC Port Valid Output to High-Impedance Conditions Min tISCCF tISCCH tISCCL tISCCFP tISCCHP tISCCLP tISCPSU tISCPH tISCPCO tISCPZV tISCPVZ (Note 1) (Note 1) (Note 1) (Note 2) (Note 2) (Note 2) 240 240 11 5 26 26 26 30 30 2 Max 15 MHz ns ns MHz ns ns ns ns ns ns ns Unit
Note: 1. For non-PLD Programming, Erase or in ISC by-pass mode. 2. For Program or Erase PLD only.
94/100
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PSD4256G6V
PART NUMBERING Table 74. Ordering Information Scheme
Example: PSD42 5 6 G 6 V - 10 U I I
Device Type PSD42 = Flash PSD with CPLD
SRAM Size 3 = 64Kbit 5 = 256Kbit
Flash Memory Size 5 = 4Mbit 6 = 8Mbit
I/O Count G = 52 I/O
2nd Non-Volatile Memory 2 = 256Kbit Flash Memory 6 = 512Kbit Flash Memory
Operating Voltage V = VCC = 2.7 to 3.6V
Speed 90 = 90ns 10 = 100ns 12 = 120ns
Package U = TQFP80
Temperature Range blank = 0 to 70C (Commercial) I = -40 to 85C (Industrial)
Option I = Tape & Reel Packing
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
95/100
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PSD4256G6V
PACKAGE MECHANICAL INFORMATION Figure 50. TQFP80 - 80-lead Plastic Quad Flatpack Package Outline
D D1 D2 A2
e Ne E2 E1 E b
N 1
Nd L1
A CP
c
QFP-A
Note: Drawing is not to scale.
A1
L
96/100
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
PSD4256G6V
Table 75. TQFP80 - 80-lead Plastic Quad Flatpack Package Mechanical Data
mm Symb Typ A A1 A2 b c D D1 D2 E E1 E2 e L L1 n Nd Ne CP - - - 1.40 0.22 - 14.00 12.00 9.50 14.00 12.00 9.50 0.50 0.60 1.00 3.5 Min - 0.05 1.35 0.17 0.09 - - - - - - - 0.45 - 0 80 20 20 - 0.08 - Max 1.60 0.15 1.45 0.27 0.20 - - - - - - - 0.75 - 7 Typ - - 0.055 0.009 - 0.551 0.472 0.374 0.473 0.394 0.374 0.020 0.024 0.039 3.5 Min - 0.002 0.053 0.007 0.004 - - - - - - - 0.018 - 0 80 20 20 - 0.003 Max 0.063 0.006 0.057 0.011 0.008 - - - - - - - 0.030 - 7 inches
97/100
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
PSD4256G6V
Table 76. Pin Assignments - PSD4256G6V TQFP80
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin Assign ments PD2 PD3 AD0 AD1 AD2 AD3 AD4 GND VCC AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 Pin No. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pin Assign ments PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 VCC GND PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 RESET CNTL2 Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Pin Assign ments PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 GND GND PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 CNTL0 CNTL1 Pin No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Pin Assign ments PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 VCC GND PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PD0 PD1
98/100
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PSD4256G6V
REVISION HISTORY Table 77. Document Revision History
Date 06-Aug-2001 13-Sep-2001 14-Dec-2001 06-Dec-2002 Rev. 1.0 1.1 1.2 1.3 Document written Package mechanical data updated Added 100ns specification; removed 90 and 120 ns specifications. Updated AC specification and Port C and F functions Added 90ns access time specification for 3.0 Vcc 3.6V Description of Revision
99/100
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PSD4256G6V
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2002 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. www.st.com
100/100
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

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